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Director Memory Design Engineer Jobs in Huntley, IL

Eliyan

DV - Director of Design Verification

Mundelein, IL · On-site

$138K - $169K/yr

D in Electrical Engineering, Computer Engineering, or related fields * 15+ years of experience in ... Experience with DRAM Controllers/PHYs, HBM memory interfaces, and/or optical interconnect ...

Huntleyfirst

Manager, Design Engineering

Huntley, IL · On-site

$140 - $160/hr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

The position integrates engineering design resources into a cohesive, high-performing team focused ... Customer-facing project management (direct OEM interaction, design reviews)* Proficiency with **CAD ...

Toppan

Manager, Design Engineering

Huntley, IL · On-site

$140K - $160K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

The position integrates engineering design resources into a cohesive, high-performing team focused ... Customer-facing project management (direct OEM interaction, design reviews) * Proficiency with CAD ...

Toppan

Manager, Design Engineering

Huntley, IL · On-site

$140K - $160K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

The position integrates engineering design resources into a cohesive, high-performing team focused ... Customer-facing project management (direct OEM interaction, design reviews) * Proficiency with CAD ...

Judge Group, Inc.

System Engineer

Buffalo Grove, IL · On-site

$40 - $50/hr

... design development Assemble or direct assembly of mechanical hardware and systems Use engineering software for project management, 3D modeling, mechanical layouts, and reporting Prepare technical ...

Motorola

Digital Hardware Development Engineer

Schaumburg, IL · On-site

$75K - $100K/yr

  • Medical

  • Dental

  • Retirement

As a Digital Hardware Development Engineer in our Public Safety group, you will be responsible for ... Design of digital circuits, experience with Microprocessor/Microcontroller, DSP, FPGA, and memory ...

Senior Lifestyle

Memory Care Coordinator Assistant

Elgin, IL

$19.25 - $25.75/hr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

The Memory Care Coordinator is responsible for supporting compliance with all community policies ... Recreation Programming, and Management Special Certifications: Activity Director Certified ...

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Showing results 21-40

All JobsMemory Design Engineer JobsDirector Memory Design Engineer JobsDirector Memory Design Engineer Jobs in Huntley, IL

Director Memory Design Engineer information

See Huntley, IL salary details

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$135.5K

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How much do director memory design engineer jobs pay per year?

As of Aug 16, 2026, the average yearly pay for director memory design engineer in Huntley, IL is $135,527.00, according to ZipRecruiter salary data. Most workers in this role earn between $109,300.00 and $162,700.00 per year, depending on experience, location, and employer.

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DV - Director of Design Verification

Eliyan

Mundelein, IL • On-site

$138K - $169K/yr

Full-time

Re-posted 16 hours ago

Job description

Join the leading chiplet startup! As the Director of Design Verification at Eliyan, you will lead and scale a high-performing verification team at a fast-paced startup creating technologies that fuel tomorrow’s chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. You will own the end-to-end verification strategy across multiple PHY and controller products, spanning link layer, PCS, PMA, forward error correction, and analog/mixed-signal verification flows. You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits.
Key Responsibilities:
  • Define and own the verification strategy and methodology across multiple PHY and controller product lines, including D2D, UCIe, and Ethernet interfaces
  • Build, mentor, and manage a world-class verification team; establish best practices for UVM-based environments, coverage-driven verification, and formal methods
  • Drive verification planning and execution for link layer, PCS, PMA, forward error correction (FEC), auto-negotiation, and link training subsystems
  • Establish and champion analog/mixed-signal (AMS) verification flows, including real-number modeling (RNM), SVAMS co-simulation strategies, and integration of AMS behavioral models into digital verification environments
  • Partner with design, architecture, DFT, and physical design teams to drive micro-architecture reviews, test-plan completeness, and functional/code/assertion coverage closure
  • Own verification milestones and deliverables across multiple concurrent tapeout programs; track progress, manage risk, and report status to executive leadership
  • Drive continuous improvement in verification infrastructure including regression frameworks, CI/CD integration, coverage analytics, and productivity tooling
  • Ensure IP compliance with relevant industry standards including IEEE 802.3, UCIe, and emerging D2D interconnect specifications
  • Evaluate, integrate, and manage 3rd party VIPs and AMS verification IP; coordinate feature/bug tracking and vendor relationships
  • Oversee development of DPI-based firmware co-simulation environments and system-level verification strategies for PHY bring-up and validation
  • Oversee GLS environments for functional, timing, and power-aware simulations; drive signoff quality for tapeout readiness
Qualifications:
  • Masters or Ph.D in Electrical Engineering, Computer Engineering, or related fields
  • 15+ years of experience in design verification of high-speed serial interfaces, PHYs, and controller IPs, with at least 5 years in a people-management or leadership role
  • Deep expertise in SystemVerilog/UVM methodology, constrained-random verification, assertion-based verification, and formal verification techniques
  • Demonstrated experience with AMS verification methodologies including real-number modeling (RNM), Verilog-AMS, SVAMS co-simulation, and mixed-signal behavioral modeling
  • Strong working knowledge of link layer protocols, PCS architectures (including FEC — RS-FEC, KP4, KR4), Ethernet 802.3 clauses for 100G/200G/400G/800G, and die-to-die interconnect standards such as UCIe
  • Proven ability to drive verification innovation including automation, AI/ML-assisted verification, and scalable methodologies that improve team productivity and product quality
  • Hands-on experience verifying mixed-signal IPs (PLLs, CDRs, SerDes analog front-ends, DLLs) and integrating analog models into digital verification environments
  • Track record of successfully building and scaling verification teams in startup or high-growth environments with multiple concurrent tapeouts
  • Experience with DRAM Controllers/PHYs, HBM memory interfaces, and/or optical interconnect verification a plus

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.