SOC DFT Intern - Spring 2027
$14.75 - $19.75/hr
DFT Engineer / Manager About the Role: We are seeking a highly motivated and detail-oriented Design ... Collaborate with RTL designers and verification teams to ensure testability requirements are met.
$14.75 - $19.75/hr
DFT Engineer / Manager About the Role: We are seeking a highly motivated and detail-oriented Design ... Collaborate with RTL designers and verification teams to ensure testability requirements are met.
$14.75 - $19.75/hr
DFT Engineer / Manager About the Role: We are seeking a highly motivated and detail-oriented Design ... Collaborate with RTL designers and verification teams to ensure testability requirements are met.
San Jose, CA · On-site
... verification and coverage analysis * Experience working with Mentor/Siemens DFT Tessent tool for ... Must be a self‑driven engineer with good project management and organizational skills to deliver ...
San Jose, CA · On-site
... verification and coverage analysis * Experience working with Mentor/Siemens DFT Tessent tool for ... Must be a self‑driven engineer with good project management and organizational skills to deliver ...
Collaborate with design, verification, packaging, and product engineering teams to optimize test ... Built-in Self-Repair (BISR) for redundancy management * Drive fault coverage targets (>99% stuck-at ...
Collaborate with design, verification, packaging, and product engineering teams to optimize test ... Built-in Self-Repair (BISR) for redundancy management * Drive fault coverage targets (>99% stuck-at ...
OR · On-site +1
$190K - $285K/yr
... DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ... Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and ...
OR · On-site +1
$190K - $285K/yr
... DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ... Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and ...
Collaborate with design, verification, packaging, and product engineering teams to optimize test ... Built-in Self-Repair (BISR) for redundancy management * Drive fault coverage targets (>99% stuck-at ...
Collaborate with design, verification, packaging, and product engineering teams to optimize test ... Built-in Self-Repair (BISR) for redundancy management * Drive fault coverage targets (>99% stuck-at ...
San Diego, CA · On-site
$144K - $148K/yr
Collaborate with cross-functional teams including RTL Design, Physical Design, Verification, DFT ... Proven experience developing and managing complex hierarchical SDC constraints for large SoCs with ...
San Diego, CA · On-site
$144K - $148K/yr
Collaborate with cross-functional teams including RTL Design, Physical Design, Verification, DFT ... Proven experience developing and managing complex hierarchical SDC constraints for large SoCs with ...
San Jose, CA · On-site
$231K - $358K/yr
... verification, and physical design teams to make sure the architecture you've defined actually holds up in silicon. You'll also be a technical anchor for the broader DFT team - not managing them on ...
San Jose, CA · On-site
$231K - $358K/yr
... verification, and physical design teams to make sure the architecture you've defined actually holds up in silicon. You'll also be a technical anchor for the broader DFT team - not managing them on ...
San Jose, CA · On-site
Scan flow development, ATPG pattern generation, verification and coverage analysis * Experience ... Must be a self‑driven engineer with good project management and organizational skills to deliver ...
San Jose, CA · On-site
Scan flow development, ATPG pattern generation, verification and coverage analysis * Experience ... Must be a self‑driven engineer with good project management and organizational skills to deliver ...
San Jose, CA · On-site
Scan flow development, ATPG pattern generation, verification and coverage analysis * Experience ... Must be a self-driven engineer with good project management and organizational skills to deliver ...
San Jose, CA · On-site
Scan flow development, ATPG pattern generation, verification and coverage analysis * Experience ... Must be a self-driven engineer with good project management and organizational skills to deliver ...
San Jose, CA · On-site
Scan flow development, ATPG pattern generation, verification and coverage analysis * Experience ... Must be a self-driven engineer with good project management and organizational skills to deliver ...
San Jose, CA · On-site
Scan flow development, ATPG pattern generation, verification and coverage analysis * Experience ... Must be a self-driven engineer with good project management and organizational skills to deliver ...
San Jose, CA · On-site
$231K - $358K/yr
... verification, and physical design teams to make sure the architecture you've defined actually holds up in silicon. You'll also be a technical anchor for the broader DFT team -- not managing them on ...
Quick apply
San Jose, CA · On-site
$231K - $358K/yr
... verification, and physical design teams to make sure the architecture you've defined actually holds up in silicon. You'll also be a technical anchor for the broader DFT team -- not managing them on ...
Seattle, WA · On-site
$190K - $285K/yr
... DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ... Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and ...
Seattle, WA · On-site
$190K - $285K/yr
... DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ... Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and ...
San Diego, CA · On-site
$144K - $148K/yr
Collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure successful ... DFT-aware physical implementation and constraint management.* Programming and automation using ...
San Diego, CA · On-site
$144K - $148K/yr
Collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure successful ... DFT-aware physical implementation and constraint management.* Programming and automation using ...
$231K - $358K/yr
... verification, and physical design teams to make sure the architecture you've defined actually holds up in silicon. You'll also be a technical anchor for the broader DFT team -- not managing them on ...
$231K - $358K/yr
... verification, and physical design teams to make sure the architecture you've defined actually holds up in silicon. You'll also be a technical anchor for the broader DFT team -- not managing them on ...
Coverage Modeling & Verification: Model structural and functional coverage to report gaps against ... manager to resolve coverage gaps via test point additions, chain corrections, or agreed ...
Coverage Modeling & Verification: Model structural and functional coverage to report gaps against ... manager to resolve coverage gaps via test point additions, chain corrections, or agreed ...
Richardson, TX · On-site
Coverage Modeling & Verification: Model structural and functional coverage to report gaps against ... manager to resolve coverage gaps via test point additions, chain corrections, or agreed ...
Richardson, TX · On-site
Coverage Modeling & Verification: Model structural and functional coverage to report gaps against ... manager to resolve coverage gaps via test point additions, chain corrections, or agreed ...
Coverage Modeling & Verification: Model structural and functional coverage to report gaps against ... manager to resolve coverage gaps via test point additions, chain corrections, or agreed ...
Coverage Modeling & Verification: Model structural and functional coverage to report gaps against ... manager to resolve coverage gaps via test point additions, chain corrections, or agreed ...
$100K - $103K/yr
Collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure successful ... DFT-aware physical implementation and constraint management.* Programming and automation using ...
$100K - $103K/yr
Collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure successful ... DFT-aware physical implementation and constraint management.* Programming and automation using ...
Los Angeles, CA · On-site
$190K - $285K/yr
... DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ... Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and ...
Quick apply
Los Angeles, CA · On-site
$190K - $285K/yr
... DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ... Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and ...
Mountain View, CA · On-site
$175K - $400K/yr
... management, high-speed connectivity and other key technologies in leading-edge process nodes. What ... Execute DFT implementation and verification flows for block-level DFT insertion , including scan ...
Mountain View, CA · On-site
$175K - $400K/yr
... management, high-speed connectivity and other key technologies in leading-edge process nodes. What ... Execute DFT implementation and verification flows for block-level DFT insertion , including scan ...
$31K - $37.8K
6% of jobs
$37.8K - $44.6K
12% of jobs
$46.9K is the 25th percentile. Wages below this are outliers.
$44.6K - $51.5K
21% of jobs
The median wage is $56.2K / yr.
$51.5K - $58.3K
16% of jobs
$58.3K - $65.1K
9% of jobs
$65.1K - $71.9K
7% of jobs
$74.7K is the 75th percentile. Wages above this are outliers.
$71.9K - $78.7K
8% of jobs
$78.7K - $85.5K
7% of jobs
$85.5K - $92.4K
5% of jobs
$92.4K - $99.2K
3% of jobs
$99.2K - $106K
4% of jobs
$31K
$63.9K
$106K
For Dft Verification Manager jobs, the most frequently searched job titles are:
Austin, TX
$14.75 - $19.75/hr
Full-time
Posted 7 days ago
Location:Austin, TX (On-site/Hybrid)
Department:Digital Design - DFT
Reports To:DFT Engineer / Manager
We are seeking a highly motivated and detail-orientedDesign for Test (DFT) Internto join our Digital Design team. As a DFT Intern, you will work closely with experienced engineers to support the development and implementation of DFT methodologies for cutting-edge SoC designs. This internship offers hands-on experience in scan insertion, ATPG, MBIST, and other test-related flows in a real-world semiconductor environment.
Key Responsibilities:Assist in the implementation of DFT techniques such as scan insertion, boundary scan, and memory BIST.
Support ATPG pattern generation and validation using industry-standard tools.
Help with test coverage analysis and debug of test patterns.
Collaborate with RTL designers and verification teams to ensure testability requirements are met.
Contribute to automation of DFT flows using scripting languages (e.g., Python, Perl, TCL).
Document DFT methodologies, test plans, and results.
Currently pursuing aBachelor's or Master's degreein Electrical Engineering, Computer Engineering, or a related field.
Strong understanding of digital logic design and VLSI fundamentals.
Familiarity with Verilog/VHDL and scripting languages (Python, Perl, or TCL).
Exposure to DFT concepts such as scan chains, ATPG, and BIST is a plus.
Experience with EDA tools from Synopsys, Cadence, or Mentor Graphics is desirable.
Excellent problem-solving skills and attention to detail.
Strong communication and teamwork abilities.
Coursework or project experience in DFT or digital IC design.
Knowledge of STA, synthesis, and RTL verification.
Familiarity with Linux/Unix environments.
Hands-on experience with industry-standard DFT tools and flows.
Mentorship from experienced engineers in a collaborative environment.
Exposure to the full ASIC design and test cycle.
Opportunity to contribute to real silicon projects.
In order to be considered for a spring internship with NXP you must be returning to school or graduating at the conclusion of the internship term. If you are graduating prior to May 2027 please apply to Entry Level full-time roles.
More information about NXP in the United States...
NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.
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