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Dft Verification Manager Jobs (NOW HIRING)

SOC DFT Intern - Spring 2027

Austin, TX

$14.75 - $19.75/hr

DFT Engineer / Manager About the Role: We are seeking a highly motivated and detail-oriented Design ... Collaborate with RTL designers and verification teams to ensure testability requirements are met.

... verification and coverage analysis * Experience working with Mentor/Siemens DFT Tessent tool for ... Must be a self‑driven engineer with good project management and organizational skills to deliver ...

Principal ASIC Design Verification Engineer

OR · On-site +1

$190K - $285K/yr

... DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ... Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and ...

Senior SoC STA Engineer

San Diego, CA · On-site

$144K - $148K/yr

Collaborate with cross-functional teams including RTL Design, Physical Design, Verification, DFT ... Proven experience developing and managing complex hierarchical SDC constraints for large SoCs with ...

Scan flow development, ATPG pattern generation, verification and coverage analysis * Experience ... Must be a self‑driven engineer with good project management and organizational skills to deliver ...

Scan flow development, ATPG pattern generation, verification and coverage analysis * Experience ... Must be a self-driven engineer with good project management and organizational skills to deliver ...

Scan flow development, ATPG pattern generation, verification and coverage analysis * Experience ... Must be a self-driven engineer with good project management and organizational skills to deliver ...

Coverage Modeling & Verification: Model structural and functional coverage to report gaps against ... manager to resolve coverage gaps via test point additions, chain corrections, or agreed ...

$100K - $103K/yr

Collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure successful ... DFT-aware physical implementation and constraint management.* Programming and automation using ...

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Dft Verification Manager information

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How much do dft verification manager jobs pay per year?

As of Sep 15, 2026, the average yearly pay for dft verification manager in the United States is $63,928.00, according to ZipRecruiter salary data. Most workers in this role earn between $47,000.00 and $78,500.00 per year, depending on experience, location, and employer.

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SOC DFT Intern - Spring 2027

Austin, TX

$14.75 - $19.75/hr

Full-time

Posted 7 days ago


Job description

Job Title:DFT Intern

Location:Austin, TX (On-site/Hybrid)
Department:Digital Design - DFT
Reports To:DFT Engineer / Manager

About the Role:

We are seeking a highly motivated and detail-orientedDesign for Test (DFT) Internto join our Digital Design team. As a DFT Intern, you will work closely with experienced engineers to support the development and implementation of DFT methodologies for cutting-edge SoC designs. This internship offers hands-on experience in scan insertion, ATPG, MBIST, and other test-related flows in a real-world semiconductor environment.

Key Responsibilities:
  • Assist in the implementation of DFT techniques such as scan insertion, boundary scan, and memory BIST.

  • Support ATPG pattern generation and validation using industry-standard tools.

  • Help with test coverage analysis and debug of test patterns.

  • Collaborate with RTL designers and verification teams to ensure testability requirements are met.

  • Contribute to automation of DFT flows using scripting languages (e.g., Python, Perl, TCL).

  • Document DFT methodologies, test plans, and results.

Qualifications:
  • Currently pursuing aBachelor's or Master's degreein Electrical Engineering, Computer Engineering, or a related field.

  • Strong understanding of digital logic design and VLSI fundamentals.

  • Familiarity with Verilog/VHDL and scripting languages (Python, Perl, or TCL).

  • Exposure to DFT concepts such as scan chains, ATPG, and BIST is a plus.

  • Experience with EDA tools from Synopsys, Cadence, or Mentor Graphics is desirable.

  • Excellent problem-solving skills and attention to detail.

  • Strong communication and teamwork abilities.

Preferred Skills (Nice to Have):
  • Coursework or project experience in DFT or digital IC design.

  • Knowledge of STA, synthesis, and RTL verification.

  • Familiarity with Linux/Unix environments.

What You'll Gain:
  • Hands-on experience with industry-standard DFT tools and flows.

  • Mentorship from experienced engineers in a collaborative environment.

  • Exposure to the full ASIC design and test cycle.

  • Opportunity to contribute to real silicon projects.

In order to be considered for a spring internship with NXP you must be returning to school or graduating at the conclusion of the internship term. If you are graduating prior to May 2027 please apply to Entry Level full-time roles.

More information about NXP in the United States...

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.

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