Sr. ASIC DFT Engineer (Silicon)
$145K - $175K/yr
SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Experience with cell-aware fault models in ATPG * Excellent problem-solving skills, with the ...
$145K - $175K/yr
SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Experience with cell-aware fault models in ATPG * Excellent problem-solving skills, with the ...
$145K - $175K/yr
SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Experience with cell-aware fault models in ATPG * Excellent problem-solving skills, with the ...
Irvine, CA · On-site
$145K - $175K/yr
Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ... Experience with cell-aware fault models in ATPG * Excellent problem-solving skills, with the ...
Irvine, CA · On-site
$145K - $175K/yr
Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ... Experience with cell-aware fault models in ATPG * Excellent problem-solving skills, with the ...
San Jose, CA · On-site
$210K - $305K/yr
Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
San Jose, CA · On-site
$210K - $305K/yr
Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
San Jose, CA · On-site
$183K - $263K/yr
Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
San Jose, CA · On-site
$183K - $263K/yr
Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
Seattle, WA · On-site
$183K - $263K/yr
... fault models, drive scan-based diagnosis methodology for Silicon failure debug, and provide post ... Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems * Perform ...
Seattle, WA · On-site
$183K - $263K/yr
... fault models, drive scan-based diagnosis methodology for Silicon failure debug, and provide post ... Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems * Perform ...
PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows.
PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows.
Austin, TX · On-site
... DFT modeling.- Work with layout team to create optimal GDS.- Verify extracted GDS meets design specifications.- Backend verification, IR/EM.- Write RTL, validate use-cases, verify against design ...
Austin, TX · On-site
... DFT modeling.- Work with layout team to create optimal GDS.- Verify extracted GDS meets design specifications.- Backend verification, IR/EM.- Write RTL, validate use-cases, verify against design ...
Sunnyvale, CA · On-site
$155K - $185K/yr
Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ... Experience with cell-aware fault models in ATPG * Excellent problem-solving skills, with the ...
Sunnyvale, CA · On-site
$155K - $185K/yr
Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ... Experience with cell-aware fault models in ATPG * Excellent problem-solving skills, with the ...
Develop and debug ATPG patterns targeting stuck-at, transition, and additional fault models ... Support clock DFT and clock verification , including clock controllability, observability, and at ...
Develop and debug ATPG patterns targeting stuck-at, transition, and additional fault models ... Support clock DFT and clock verification , including clock controllability, observability, and at ...
Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification] Location : Santa Clara, CA ... Develop and debug ATPG patterns targeting stuck‑at, transition, and additional fault models
Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification] Location : Santa Clara, CA ... Develop and debug ATPG patterns targeting stuck‑at, transition, and additional fault models
San Jose, CA · On-site
$183K - $263K/yr
Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
San Jose, CA · On-site
$183K - $263K/yr
Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
San Jose, CA · On-site
$210K - $305K/yr
Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
San Jose, CA · On-site
$210K - $305K/yr
Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
Develop and debug ATPG patterns targeting stuck-at, transition, and additional fault models ... Support clock DFT and clock verification , including clock controllability, observability, and at ...
Develop and debug ATPG patterns targeting stuck-at, transition, and additional fault models ... Support clock DFT and clock verification , including clock controllability, observability, and at ...
Maynard, MA · On-site
$183K - $263K/yr
... fault models, drive scan-based diagnosis methodology for Silicon failure debug, and provide post ... Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems * Perform ...
Maynard, MA · On-site
$183K - $263K/yr
... fault models, drive scan-based diagnosis methodology for Silicon failure debug, and provide post ... Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems * Perform ...
San Jose, CA · On-site
$210K - $305K/yr
Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
San Jose, CA · On-site
$210K - $305K/yr
Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
$183K - $263K/yr
... fault models, drive scan-based diagnosis methodology for Silicon failure debug, and provide post ... Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems * Perform ...
$183K - $263K/yr
... fault models, drive scan-based diagnosis methodology for Silicon failure debug, and provide post ... Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems * Perform ...
San Jose, CA · On-site
$183K - $263K/yr
... fault models, drive scan-based diagnosis methodology for Silicon failure debug, and provide post ... Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems * Perform ...
San Jose, CA · On-site
$183K - $263K/yr
... fault models, drive scan-based diagnosis methodology for Silicon failure debug, and provide post ... Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems * Perform ...
$200K - $285K/yr
PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows.
$200K - $285K/yr
PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows.
$200K - $285K/yr
PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows.
$200K - $285K/yr
PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows.
$210K - $305K/yr
Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
$210K - $305K/yr
Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
| Aspect | Dft Modeling | Dft Design |
|---|---|---|
| Primary Focus | Creating and validating design-for-testability models to ensure testability of integrated circuits | Designing the actual testability features and structures within the chip during the design process |
| Required Skills | Knowledge of test methodologies, EDA tools, and circuit design | Circuit design, testability principles, and EDA tool proficiency |
| Work Environment | Typically in semiconductor or electronics companies, working closely with design and test teams | In design teams, focusing on integrating test features into chip architecture |
While Dft Modeling involves creating models to verify testability, Dft Design focuses on embedding test features during the design phase. Both roles require similar skills and often collaborate closely to ensure chips are testable and manufacturable efficiently.

$145K - $175K/yr
Other
Medical, Dental, Vision, Life, Retirement, PTO
Posted 9 days ago
8.7
Based on 143 frontline employees who took The Breakroom Quiz
12th of 59 rated aerospace companies
SR. ASIC DFT ENGINEER (SILICON ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering and ASIC implementation). In this role, you will be developing next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
BASIC QUALIFICATIONS:
PREFERRED SKILLS AND EXPERIENCE:
ADDITIONAL REQUIREMENTS:
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.
Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.
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Accounting services
1,001 - 5,000 Employees
Hawthorne, CA, US
2002