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Dft Modeling Jobs (NOW HIRING)

SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Experience with cell-aware fault models in ATPG * Excellent problem-solving skills, with the ...

Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ... Experience with cell-aware fault models in ATPG * Excellent problem-solving skills, with the ...

ASIC Technical Lead- DFT

San Jose, CA · On-site

$210K - $305K/yr

Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.

... fault models, drive scan-based diagnosis methodology for Silicon failure debug, and provide post ... Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems * Perform ...

... DFT modeling.- Work with layout team to create optimal GDS.- Verify extracted GDS meets design specifications.- Backend verification, IR/EM.- Write RTL, validate use-cases, verify against design ...

Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ... Experience with cell-aware fault models in ATPG * Excellent problem-solving skills, with the ...

Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.

... fault models, drive scan-based diagnosis methodology for Silicon failure debug, and provide post ... Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems * Perform ...

Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.

... fault models, drive scan-based diagnosis methodology for Silicon failure debug, and provide post ... Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems * Perform ...

... fault models, drive scan-based diagnosis methodology for Silicon failure debug, and provide post ... Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems * Perform ...

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Dft Modeling information

What are some common challenges faced by DFT Modeling engineers during chip design projects?

DFT (Design for Test) Modeling engineers often encounter challenges such as integrating testability features without impacting overall chip performance, coordinating with multiple design teams to ensure test logic compatibility, and keeping up with evolving industry standards. Balancing the need for thorough test coverage with area, power, and timing constraints can be complex. Additionally, collaborating closely with verification, RTL, and physical design teams is crucial to resolve issues early and streamline the test insertion process.

What is DFT modeling?

DFT modeling, or Density Functional Theory modeling, is a computational chemistry method used to investigate the electronic structure of molecules and materials. It allows scientists to predict properties like energy levels, molecular geometries, and reaction mechanisms using quantum mechanical principles. DFT is widely used because it provides a good balance between accuracy and computational cost, making it suitable for studying complex chemical systems. Researchers in fields such as chemistry, physics, and materials science commonly use DFT modeling to gain insights that are difficult to obtain through experiments alone.

What are the key skills and qualifications needed to thrive as a DFT Modeling Engineer, and why are they important?

To thrive as a DFT (Design for Test) Modeling Engineer, you need a strong background in digital electronics, test methodologies, and a relevant degree in electrical or computer engineering. Familiarity with EDA tools like Synopsys DFT Compiler, Mentor Tessent, scripting languages (Python, TCL), and knowledge of standards like IEEE 1149.x are typically required. Analytical thinking, attention to detail, and effective communication are crucial soft skills for collaborating with design and verification teams. These competencies ensure robust testability of complex chips, reducing manufacturing defects and ensuring product reliability.

What is the difference between Dft Modeling vs Dft Design?

AspectDft ModelingDft Design
Primary FocusCreating and validating design-for-testability models to ensure testability of integrated circuitsDesigning the actual testability features and structures within the chip during the design process
Required SkillsKnowledge of test methodologies, EDA tools, and circuit designCircuit design, testability principles, and EDA tool proficiency
Work EnvironmentTypically in semiconductor or electronics companies, working closely with design and test teamsIn design teams, focusing on integrating test features into chip architecture

While Dft Modeling involves creating models to verify testability, Dft Design focuses on embedding test features during the design phase. Both roles require similar skills and often collaborate closely to ensure chips are testable and manufacturable efficiently.

Infographic showing various Dft Modeling job openings in the United States as of May 2026, with employment types broken down into 100% Full Time. Highlights an 84% Physical, 4% Hybrid, and 12% Remote job distribution.
Sr. ASIC DFT Engineer (Silicon)

Sr. ASIC DFT Engineer (Silicon)

SpaceX

Irvine, CA

$145K - $175K/yr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Posted 9 days ago


SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 143 frontline employees who took The Breakroom Quiz

12th of 59 rated aerospace companies


Job description

SR. ASIC DFT ENGINEER (SILICON ENGINEERING)

At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering and ASIC implementation). In this role, you will be developing next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

  • Implement and optimize DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools
  • Integration and verification of Design for Test (DFT) IPs and fabrics within Subsystems
  • Set up and run Automatic Test Pattern Generation (ATPG) tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows.
  • Run and debug non-timing and SDF annotated gate-level simulations
  • Create and validate DFT patterns for post-silicon bringup and also help with ATE debug through all cycles of silicon characterization
  • Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl, or C++

BASIC QUALIFICATIONS:

  • Bachelor's degree in electrical engineering, computer engineering, or physics
  • 5+ years of experience in semiconductor Design For Test (DFT) engineering, post-silicon validation, and/or production testing

PREFERRED SKILLS AND EXPERIENCE:

  • Master's or PhD in electrical engineering, computer engineering, physics, or related engineering field
  • Extensive experience in post-silicon bringup, including silicon debug, failure analysis, and yield optimization on complex SoCs or ASICs
  • Hands-on experience with Automated Test Equipment (ATE) platforms (e.g., Teradyne, Advantest) for high-volume manufacturing test development and debug
  • Experience collaborating with cross-functional teams (e.g., design, verification, and manufacturing) to ensure DFT features meet production requirements, utilizing Siemens Tessent workflows
  • Knowledge of industry standards for testability (e.g., IEEE 1500, 1687) and experience with low-power DFT techniques using Siemens Tessent
  • Experience with In-System Test (IST), boundary scan (IEEE 1149.1), functional testing in embedded systems, or board-level diagnostics, preferably using Siemens Tessent tools
  • Hands-on experience with Tessent Streaming Scan Network
  • Experience with cell-aware fault models in ATPG
  • Excellent problem-solving skills, with the ability to analyze complex test failures and implement corrective actions
  • Strong communication skills for documenting test strategies, reporting results, and presenting to stakeholders
  • Ability to work in a fast-paced environment, handling multiple projects and adapting to evolving technology nodes (e.g., 7nm and below)

ADDITIONAL REQUIREMENTS:    

  • Ability to work extended hours and weekends as needed to meet critical milestones
COMPENSATION AND BENEFITS:
Pay Range:
Level 1: $125,000 - $150,000
Level 2: $145,000 - $175,000

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.


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