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Dft Modeling Jobs (NOW HIRING)

Etched

DFT Intern

San Jose, CA · On-site

Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF) * Exposure to DFT flow automation or ... regression infrastructure * Familiarity with clocking and reset schemes We encourage you to apply ...

Etched

DFT Intern

San Jose, CA · On-site

Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF) * Exposure to DFT flow automation or ... regression infrastructure * Familiarity with clocking and reset schemes We encourage you to apply ...

Intellectt INC

DFT Engineers

Santa Clara, CA · On-site

DFT Engineers Location: Santa Clara, California We are looking for a DFT / ATPG Engineer with ... DRC debug and fault model validation * Generating test timing and PnR collaterals * Expertise in ...

Intellectt INC

DFT Engineers

Santa Clara, CA · On-site

DFT Engineers Location: Santa Clara, California : * 5+ years of hands-on experience in DFT and ATPG ... Pattern Generation for different fault models Qualification: BE Thanks Regards, JAYADEV Sourcing ...

Intellectt INC

DFT Engineers

Santa Clara, CA · On-site

DFT Engineers Location: Santa Clara, California We are looking for a DFT / ATPG Engineer with ... DRC debug and fault model validation * Generating test timing and PnR collaterals * Expertise in ...

Purple Hires Inc

Lead ASIC DFT Engineer

Plano, TX · Remote

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies ...

New

Altera

DFT Architect

San Jose, CA · On-site

$187K - $270K/yr

Experience with SSN, test compression, BIST (MBIST/LBIST), and advanced fault models. * Prior experience with 2.5D/3D multi-die designs and high-speed IO/SerDes DFT. Job Type: Regular Shift: Shift 1 ...

Altera Corporation

DFT Architect

San Jose, CA · On-site

$187K - $270K/yr

Experience with SSN, test compression, BIST (MBIST/LBIST), and advanced fault models. * Prior experience with 2.5D/3D multi-die designs and high-speed IO/SerDes DFT. Job Type: Regular Shift: Shift 1 ...

K2 Space

OR

$170K - $250K/yr

Deep understanding of scan architectures, compression techniques, fault models (stuck-at, transition, bridging, path delay), coverage analysis and closure strategies. * Experience with low-power DFT ...

Cisco Systems, Inc.

ASIC DFT Engineer

San Jose, CA

Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.

Etched

DFT (Design For Test) Engineer

San Jose, CA · On-site

$150K - $275K/yr

... models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of ... Develop and implement robust Design for Test (DFT) architectures for ASIC and SoC designs to ...

USM

JB061568 - Lead ASIC DFT Engineer

San Jose, CA · On-site

$194K/yr

Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts. * Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.

K2 Space

Senior DFT Engineer

$170K - $250K/yr

Deep understanding of scan architectures, compression techniques, fault models (stuck-at, transition, bridging, path delay), coverage analysis and closure strategies. * Experience with low-power DFT ...

Etched

DFT (Design For Test) Engineer

San Jose, CA · On-site

$150K - $275K/yr

... models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of ... Develop and implement robust Design for Test (DFT) architectures for ASIC and SoC designs to ...

K2 Space

Senior DFT Engineer

Los Angeles, CA · On-site

$170K - $250K/yr

Deep understanding of scan architectures, compression techniques, fault models (stuck-at, transition, bridging, path delay), coverage analysis and closure strategies. * Experience with low-power DFT ...

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Dft Modeling information

What are some common challenges faced by DFT Modeling engineers during chip design projects?

DFT (Design for Test) Modeling engineers often encounter challenges such as integrating testability features without impacting overall chip performance, coordinating with multiple design teams to ensure test logic compatibility, and keeping up with evolving industry standards. Balancing the need for thorough test coverage with area, power, and timing constraints can be complex. Additionally, collaborating closely with verification, RTL, and physical design teams is crucial to resolve issues early and streamline the test insertion process.

What is DFT modeling?

DFT modeling, or Density Functional Theory modeling, is a computational chemistry method used to investigate the electronic structure of molecules and materials. It allows scientists to predict properties like energy levels, molecular geometries, and reaction mechanisms using quantum mechanical principles. DFT is widely used because it provides a good balance between accuracy and computational cost, making it suitable for studying complex chemical systems. Researchers in fields such as chemistry, physics, and materials science commonly use DFT modeling to gain insights that are difficult to obtain through experiments alone.

What are the key skills and qualifications needed to thrive as a DFT Modeling Engineer, and why are they important?

To thrive as a DFT (Design for Test) Modeling Engineer, you need a strong background in digital electronics, test methodologies, and a relevant degree in electrical or computer engineering. Familiarity with EDA tools like Synopsys DFT Compiler, Mentor Tessent, scripting languages (Python, TCL), and knowledge of standards like IEEE 1149.x are typically required. Analytical thinking, attention to detail, and effective communication are crucial soft skills for collaborating with design and verification teams. These competencies ensure robust testability of complex chips, reducing manufacturing defects and ensuring product reliability.

What is the difference between Dft Modeling vs Dft Design?

AspectDft ModelingDft Design
Primary FocusCreating and validating design-for-testability models to ensure testability of integrated circuitsDesigning the actual testability features and structures within the chip during the design process
Required SkillsKnowledge of test methodologies, EDA tools, and circuit designCircuit design, testability principles, and EDA tool proficiency
Work EnvironmentTypically in semiconductor or electronics companies, working closely with design and test teamsIn design teams, focusing on integrating test features into chip architecture

While Dft Modeling involves creating models to verify testability, Dft Design focuses on embedding test features during the design phase. Both roles require similar skills and often collaborate closely to ensure chips are testable and manufacturable efficiently.

Infographic showing various Dft Modeling job openings in the United States as of May 2026, with employment types broken down into 100% Full Time. Highlights an 84% Physical, 4% Hybrid, and 12% Remote job distribution.

DFT Intern

Etched

San Jose, CA • On-site

Other

Posted 24 days ago

Job description

About Etched

Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

As a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression on Caelius. You will work across frontend and backend design teams, contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations), and develop flows for various ATPG fault models. You do not necessarily need prior DFT experience; just the ability to learn quickly in a fast-paced, high-autonomy environment. We are looking for Summer '26, Fall '26, Spring '27, and Summer '27 interns.

You may be a good fit if you have

  • Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field.

  • Familiarity with a hardware description language (Verilog or SystemVerilog)

  • Exposure to ASIC or SoC design concepts

  • Familiarity with digital logic design fundamentals

  • Familiarity with standard ASIC design flow steps (synthesis, STA, DFT)

  • Familiarity with scripting in Python, Tcl, or another language

  • Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Strong candidates may also have experience with

  • Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression

  • Experience with Tessent or similar DFT tooling

  • Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF)

  • Exposure to DFT flow automation or regression infrastructure

  • Familiarity with clocking and reset schemes

We encourage you to apply even if you do not believe you meet every single qualification.

Program details

  • 12-week paid internship

  • Generous housing support for those relocating

  • Daily lunch and dinner in our office

  • Based at our office in San Jose, CA

  • Direct mentorship from industry leaders and world-class engineers

  • Opportunity to work on one of the most important problems of our time

For any questions, contact internships@etched.com.

How we’re different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.