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Dft Engineer Jobs in Texas (NOW HIRING)

Micron

New College Grad - Design Engineer, HBM DFT

Richardson, TX · On-site

$90K - $124K/yr

  • Medical

  • Dental

  • Vision

  • PTO

As part of the Design for Test (DFT) Engineering team, this role contributes to enabling testability and quality for next-generation High Bandwidth Memory (HBM) products. The team focuses on ...

Ambiq Micro, Inc.

Sr. Staff Engineer - DFT

Austin, TX · On-site

Scope We are seeking an experienced DFT (Design for Testability) Engineer to design, implement, and optimize test architectures for semiconductor products. This role involves collaborating with ...

Intel

DFT Implementation Engineer

Austin, TX · On-site

$141K - $200K/yr

  • Medical

  • Retirement

  • PTO

The Role and Impact As a DFT Design Engineer, you will play a pivotal role in shaping Intel's silicon solutions. Your contributions will directly influence the quality and efficiency of Intel ...

Intel Corporation

DFT Implementation Engineer

Austin, TX · On-site

$141K - $200K/yr

  • Medical

  • Retirement

  • PTO

The Role and Impact As a DFT Design Engineer, you will play a pivotal role in shaping Intel's silicon solutions. Your contributions will directly influence the quality and efficiency of Intel ...

Apple

GPU DFT Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

The DFT Design Verification Engineer will be on a team which is responsible for the complete DFT pre-silicon verification and support for silicon bring-up of GPU core. Description As a DFT ...

Apple

GPU DFT Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

The DFT Design Verification Engineer will be on a team which is responsible for the complete DFT pre-silicon verification and support for silicon bring-up of GPU core. Description As a DFT ...

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$120.7K

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How much do dft engineer jobs pay per year?

As of Aug 13, 2026, the average yearly pay for dft engineer in Texas is $120,660.00, according to ZipRecruiter salary data. Most workers in this role earn between $96,000.00 and $125,300.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a DFT engineer?

To thrive as a DFT (Design for Test) Engineer, you need a solid background in electrical engineering, digital design, and ASIC/FPGA development, often supported by a relevant degree. Familiarity with test methodologies, scan insertion tools (such as Synopsys DFT Compiler or Mentor Tessent), and scripting languages like Perl or Python is typically required. Strong problem-solving skills, attention to detail, and effective communication help DFT Engineers collaborate with design and verification teams to resolve complex testability challenges. These competencies are essential to ensure high-quality, testable silicon designs that minimize defects and streamline manufacturing processes.

What is the difference between Dft Engineer vs Test Engineer?

AspectDft EngineerTest Engineer
Required CredentialsBachelor's in Electronics, Electrical, or related fields; certifications in DFT techniquesBachelor's in Electronics, Electrical, Computer Science; certifications in testing methodologies
Work EnvironmentDesign and implementation of DFT strategies during IC developmentTesting, validation, and debugging of electronic products and systems
Employer & Industry UsageSemiconductor companies, IC design firmsConsumer electronics, automotive, telecommunications industries

While both Dft Engineers and Test Engineers work in electronics and semiconductor industries, Dft Engineers focus on designing testability features during chip development, whereas Test Engineers execute testing and validation of finished products. Their roles complement each other, but their daily tasks and expertise areas differ significantly.

Is DFT engineering a good career?

DFT (Design for Test) engineering is a specialized field within semiconductor and integrated circuit design, focusing on ensuring chip testability and manufacturability. It offers steady demand due to the need for quality control in electronics manufacturing and typically requires knowledge of digital design, testing methodologies, and tools like EDA software. Career growth depends on industry trends, technical skills, and certifications, making it a viable option for those interested in hardware design and testing.

How much do DFT engineers make?

Design for Test (DFT) engineers typically earn between $80,000 and $130,000 annually, depending on experience, location, and industry. Senior DFT engineers with specialized skills in automation and verification can earn higher salaries, especially in high-demand tech regions.

What does a Dft engineer do?

A DFT (Design for Test) engineer designs and implements testing strategies to ensure integrated circuits and electronic systems are defect-free and function correctly. They develop test plans, create test hardware and software, and work closely with design teams to improve testability and reduce manufacturing defects. Proficiency in scripting, testing tools, and industry standards is essential for this role.

What are some common challenges faced by DFT engineers during the silicon validation phase, and how can these be addressed?

DFT Engineers often encounter challenges during the silicon validation phase, such as discrepancies between simulation results and actual silicon behavior, limited access to internal nodes, and diagnosing scan chain failures. These issues can be addressed by thorough pre-silicon verification, incorporating robust test points, and leveraging advanced diagnostic tools and methodologies. Effective collaboration with design and validation teams is also crucial to quickly resolve issues and implement necessary design changes, ensuring high test coverage and product reliability.

What is a DFT engineer?

DFT Engineers, or Design for Test Engineers, are professionals who specialize in designing and implementing test structures and methodologies within integrated circuits (ICs) to ensure their testability and reliability during manufacturing. Their work enables efficient detection and diagnosis of faults in chips, helping to improve yield and reduce production costs. DFT Engineers collaborate closely with design, verification, and manufacturing teams to integrate features such as scan chains, built-in self-test (BIST), and boundary scan into chip designs. Their expertise is crucial for modern semiconductor development, especially as chips become increasingly complex.
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Dft Engineer jobs near you
Infographic showing various Dft Engineer job openings in Texas as of August 2026, with employment types broken down into 92% Full Time, 3% Part Time, and 5% Contract. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution, with an average salary of $120,660 per year, or $58 per hour.

ASIC/SOC DFT Engineer (Silicon Engineering)

SpaceX

Austin, TX • On-site

$164K/yr

Full-time

Posted 6 days ago

SpaceX rating

8.8

Company rating: 8.8 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

15th of 72 rated aerospace companies

Job description

ASIC/SOC DFT ENGINEER (SILICON ENGINEERING)

At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

  • Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
  • Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
  • Running and evaluating scan insertion through synthesis tools and refining scan insertion recipe for maximum coverage
  • Run ATPG(Automatic Test Pattern Generation) analysis to ensure quality scan chain construction and meeting basic coverage goals
  • Run and debug non-timing and SDF annotated gate level simulations
  • Creating ATPG content for use in post-silicon testing and validating that content through gate level simulation
  • Collaborate with circuit physical design team, ATPG team and manufacturing team to facilitate high quality scan coverage in silicon

BASIC QUALIFICATIONS:

  • Bachelor's degree in electrical engineering, computer engineering or computer science
  • 1+ years of professional experience working with ASICs
  • Experience in scan insertion or DFT setup

PREFERRED SKILLS AND EXPERIENCE:

  • Understanding of ASIC design flow, methodologies, physical design, and verification
  • Experience with high reliability design and implementations
  • Good scripting skills (csh/bash, Perl, Python etc.)
  • Familiar with implementation or integration of design blocks using Verilog/SystemVerilog
  • Familiar with UPF (unified power format), formal verification, and DRC rule checking experience
  • Ability to work in a dynamic environment with changing needs and requirements
  • Team-player, can-do attitude, and ability to work well in a group environment while still contributing on an individual basis
  • Enjoys being challenged and learning new skills

ADDITIONAL REQUIREMENTS:

  • Must be willing to work extended hours and weekends as needed

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About SpaceX

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Industry

Aerospace product and parts manufacturing, data services, guided missile and space vehicle manufacturing and satellite telecommunications

Company size

1,001 - 5,000 Employees

Headquarters location

Hawthorne, CA, US

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