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Design Verification Engineer Jobs in Massachusetts

Analogdevices

Senior Verification Engineer

Wilmington, MA

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

About the Role Analog Devices is seeking a highly motivated Senior Design Verification Engineer to join our Security IP team developing next-generation hardware security solutions. Our technology ...

Analog Devices

Senior Verification Engineer

Wilmington, MA · On-site

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

About the Role Analog Devices is seeking a highly motivated Senior Design Verification Engineer to join our Security IP team developing next-generation hardware security solutions. Our technology ...

Lightmatter

Staff/Sr. Staff Design Verification

Boston, MA · On-site

$206K - $236K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

As a Design Verification Engineer at Lightmatter, you will find yourself at the heart of a dynamic, interdisciplinary team. Your role will involve close collaboration with our digital design experts ...

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Design Verification Engineer information

See Massachusetts salary details

$115.2K

$162.9K

$182.4K

How much do design verification engineer jobs pay per year?

As of Aug 14, 2026, the average yearly pay for design verification engineer in Massachusetts is $162,890.00, according to ZipRecruiter salary data. Most workers in this role earn between $148,500.00 and $181,300.00 per year, depending on experience, location, and employer.

What skills and qualifications are needed to be a design verification engineer?

Design Verification Engineers require a solid background in digital design concepts, computer engineering, and electrical engineering, usually supported by a relevant bachelor’s or master’s degree. Expertise with hardware description languages like Verilog or VHDL, simulation tools, and familiarity with Unix/Linux environments are typical technical requirements, with certifications in FPGA/ASIC design considered advantageous. Strong analytical thinking, problem-solving skills, teamwork, and effective communication help these engineers collaborate closely with design, validation, and development teams. These competencies are vital to ensuring design correctness, catching flaws early, and driving efficient, reliable hardware development.

What is a design verification engineer?

A Design Verification Engineer ensures that hardware designs function correctly by developing and executing test plans, writing verification code (often in SystemVerilog with UVM), and debugging design issues. They work closely with design and validation teams to confirm specifications are met before manufacturing. Their role is critical in preventing costly design flaws and ensuring high-quality semiconductor products.

What are the most common challenges faced by design verification engineers in their daily work?

Design Verification Engineers often face the challenge of thoroughly validating complex digital designs within tight project deadlines. Debugging intricate issues, dealing with evolving specifications, and ensuring complete coverage during simulation can require a great deal of attention to detail and persistence. Collaboration with designers, validation teams, and often cross-functional groups is critical to resolving ambiguities and preventing errors from reaching production. Adapting to new verification methodologies or tools is also common as technologies and standards advance. These challenges offer valuable learning opportunities and play a crucial role in producing robust, high-quality hardware products.

What are the most commonly searched types of Design Verification Engineer jobs in Massachusetts?

The most popular types of Design Verification Engineer jobs in Massachusetts are:

What are popular job titles related to Design Verification Engineer jobs in Massachusetts?

For Design Verification Engineer jobs in Massachusetts, the most frequently searched job titles are:

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Design Verification Engineer jobs near you
Infographic showing various Design Verification Engineer job openings in Massachusetts as of July 2026, with employment types broken down into 87% Full Time, 10% Part Time, and 3% Contract. Highlights an 86% Physical, 4% Hybrid, and 10% Remote job distribution, with an average salary of $162,890 per year, or $78.3 per hour.

Design Verification Engineer, Intern

Tenstorrent University Jobs

Boston, MA • On-site

Internship

Re-posted 6 days ago

Job description

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
At Tenstorrent, we believe the future of computing must be open, which is why our interns don't just watch from the sidelines - they help build the core of it. We provide a "code-to-career" pipeline where students collaborate with industry experts to solve high-stakes problems in RISC-V and AI hardware-software co-design. By joining us, you are taking an internship to democratize high-performance computers that are accessible to everyone.
As a Design Verification Engineer Intern on the SoC Digital Verification team, you will help ensure the functional correctness and robustness of Tenstorrent's next-generation RISC-V and AI accelerator SoCs. You will work on building and improving modern verification environments, developing tests and checkers, and analyzing coverage to sign off complex digital IP and subsystems. Your work directly contributes to the reliability of the chips that power our AI and high-performance computing roadmap.
We are looking for a minimum of 3 months for this role with the potential for extension to 6 months.
This role is hybrid, based in our Boston, MA office.
Who you are
  • Pursuing a B.S. , M.S. or PhD. in Electrical Engineering, Computer Engineering, Computer Science, or a related field with a focus on digital design and verification.
  • Strong understanding of digital logic design and computer architecture (pipelines, caches, interconnects, memory systems).
  • Familiar with HDLs such as Verilog/SystemVerilog, and interested in learning Formal verification, Cocotb, and UVM-based verification methodologies.
  • Comfortable working in Linux-based development environments and using scripting languages (e.g., Python, Shell, Perl) to automate tasks.
  • Detail-oriented problem solver who enjoys debugging complex issues, reasoning about corner cases, and working from specifications.
  • Collaborative team member with clear communication skills, able to document work and discuss trade-offs with RTL, architecture, and validation teams.

What We Need
  • Help develop and maintain SystemVerilog/UVM testbenches for SoC IP blocks and subsystems, including stimulus, checkers, and scoreboards.
  • Write and refine verification test plans from architectural and micro-architectural specifications, with a strong focus on corner cases and coverage.
  • Develop constrained-random and directed tests, run regressions, and triage failures by working closely with RTL designers to root-cause issues.
  • Analyze functional and code coverage results, identify gaps, and propose additional tests or checks to drive coverage closure.
  • Contribute to automation and infrastructure (scripts, Makefiles, CI hooks, dashboards) that improve verification productivity and debug turnaround time.
  • Partner with cross-functional teams (architecture, design, performance, validation) to align on expected behavior and sign-off criteria for silicon.
  • Have impact measured through coverage metrics achieved, quality and reproducibility of bugs found, and robustness of the verification environment you help build.

What You Will Learn
  • End-to-end SoC design and verification flow for cutting-edge RISC-V and AI accelerator architectures.
  • Industry-standard verification methodologies (SystemVerilog/UVM), including testbench architecture, stimulus generation, and scoreboard/checker design.
  • Hands-on experience with simulation, regression, and coverage tools used in large-scale industrial verification environments.
  • How to read and interpret hardware specifications, micro-architecture documents, and timing diagrams, and translate them into actionable tests and assertions.
  • Exposure to high-performance interconnects, memory controllers, and accelerators, and how they are verified at IP, subsystem, and SoC levels.
  • Best practices for collaborating in a silicon development team, including code review, documentation, and cross-site communication.

USA Hiring Timelines
This internship opportunity is available throughout our 3 terms with the following corresponding recruitment cycles:
  • Winter Term: Jan-Apr work term, Sept-Dec recruit.
  • Summer Term: May-Aug work term, Oct-Apr recruit.
  • Fall Term: Sept-Dec work term, Jan-Aug recruit.

Please note these timelines are for reference only. Actual timelines may vary.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

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