Ddr Memory Jobs in California (NOW HIRING)

Experience with BIOS, firmware, DDR memory, or lab bench testing is preferable. Salary Range: * $100,000-155,000+ depending on experience and location. Weekly Schedule: * Hybrid schedule (3 days ...

Define and review high-speed layout requirements for HDMI, DisplayPort, USB-C, Ethernet, PCIe, DDR memory, LVDS, MIPI, and related interfaces. * Perform signal integrity and power integrity analysis.

Own DDR5 and LPDDR5 memory subsystem validation, including defining and executing validation strategies across multiple FPGA programs. * Create, define, and develop comprehensive system-level ...

Planning and performing DDR memory tuning, validation, and feature enablement on NVIDIA products. * Reviewing silicon design specifications, component datasheets, board schematics, and layout.

Planning and performing DDR memory tuning, validation, and feature enablement on NVIDIA products. * Reviewing silicon design specifications, component datasheets, board schematics, and layout.

Senior Memory Validation Engineer DDR/HBM, Silicon Bring-up BrickRed Systems Mountain View, California, United States (On-site) We are seeking a highly experienced Senior Memory Validation Engineer ...

... DDR/Memory, Security/Boot, Low-Speed IO, and other critical technologies - that customers and ... Own and drive DDR/LPDDR/HBM subsystem micro-architecture definition, RTL implementation, and ...

... DDR/Memory, Security/Boot, Low-Speed IO, and other critical technologies - that customers and ... Own and drive DDR/LPDDR/HBM subsystem micro-architecture definition, RTL implementation, and ...

Develop and execute verification plans for high-speed memory interfaces (DDR4/DDR5, LPDDR4/LPDDR5 ... Strong knowledge of DDR, LPDDR, or HBM protocols and architecture * Expertise in System Verilog and ...

Develop and execute verification plans for high-speed memory interfaces (DDR4/DDR5, LPDDR4/LPDDR5 ... Strong knowledge of DDR, LPDDR, or HBM protocols and architecture * Expertise in System Verilog and ...

... memory subsystems ... The front end of the DDR controller interfaces to the rest of the system such as CPU, GPU, DSP ...

... memory subsystems ... The front end of the DDR controller interfaces to the rest of the system such as CPU, GPU, DSP ...

Drive end‑to‑end validation of SoC subsystems (DDR, memory controller, cache, interconnect) across: * RTL simulation (Verilog/SystemVerilog) * Emulation platforms * Post‑silicon environments

Develop, validate, and debug firmware using C and Python across Leo's PCIe/CXL and DDR memory subsystems * Spearhead internal and external discussions on design requirements of DDR4/DDR5 DRAM ...

Desirable: verification of DDR memory interfaces * Desirable: experience with analog/mixed‑signal products * Desirable: SVA (System/Verilog Assertions) * Desirable: Jenkins (CI/CD integration)

... and DDR memory Proficiency in using lab equipment such as oscilloscopes, logic Analyzer, DMM, VNA, BERT, packet generator and Thermal chamber Test plan preparation, test setup creation and test ...

Develop, validate, and debug firmware using C and Python across Leo's PCIe/CXL and DDR memory subsystems * Assist with end-to-end firmware validation of DDR4/DDR5 DRAM interfaces, including ...

Develop, validate, and debug firmware using C and Python across Leo's PCIe/CXL and DDR memory subsystems * Spearhead internal and external discussions on design requirements of DDR4/DDR5 DRAM ...

... and DDR memory. This role owns end-to-end electrical sign-off for boards, and acts as a technical authority for signal integrity, power integrity, and compliance readiness, working closely with ...

Lead sub-system validation and qualification by defining, executing, and automating comprehensive test plans across CPU, DDR memory, PCIe, and Ethernet interfaces to accelerate time-to-market.