Ddr Memory Jobs in California (NOW HIRING)

Post -Silicon Engineer - DDR Memory Location: Sunnyvale, CA JD: * HBM / DDR expert * Experience in memory validation * Understanding of memory training and understanding of memory test algorithms

Responsibilities * Serve as the technical lead for Design Verification of complex DDR memory subsystems across multiple FPGA product families. * Define and drive verification architecture ...

Responsibilities * Serve as the technical lead for Design Verification of complex DDR memory subsystems across multiple FPGA product families. * Define and drive verification architecture ...

Perform root cause analysis of memory subsystem behaviors involving DDR controllers, cache coherency mechanisms, and system-level interactions. * Collaborate with customers, OEMs, and ODMs to support ...

Perform root cause analysis of memory subsystem behaviors involving DDR controllers, cache coherency mechanisms, and system-level interactions. * Collaborate with customers, OEMs, and ODMs to support ...

Perform root cause analysis of memory subsystem behaviors involving DDR controllers, cache coherency mechanisms, and system-level interactions.Collaborate with customers, OEMs, and ODMs to support ...

The role requires expertise in SystemVerilog, HBM/LPDDR/DDR memory technologies, and timing closure. Ideal candidates will have 8+ years of experience and a BS/MS in Electrical or Computer ...

Select and interface system-on-chips (SoCs), FPGAs, DDR memory devices, Ethernet PHYs, and high-speed transceivers appropriate for performance, cost, and reliability targets. * Plan and execute bench ...

Architect high-performance HBM/DDR memory subsystems for Marvell's custom compute products, including developing specifications, performance models, and product requirements. * Define and evolve ...

Architect high-performance HBM/DDR memory subsystems for Marvell's custom compute products, including developing specifications, performance models, and product requirements. * Define and evolve ...

Architect high-performance HBM/DDR memory subsystems for Marvell's custom compute products, including developing specifications, performance models, and product requirements. * Define and evolve ...

Description This role involves the comprehensive bench-level validation, bring-up, and characterization of DDR memory interfaces within Apple's cutting-edge SoCs. You will be responsible for ...

... DDR/Memory, Security/Boot, Low-Speed IO, and other critical technologies - that customers and internal SoC teams can adopt with confidence. By shifting left, the COE enables faster time-to-market ...

Select and interface system-on-chips (SoCs), FPGAs, DDR memory devices, Ethernet PHYs, and high-speed transceivers appropriate for performance, cost, and reliability targets. * Plan and execute bench ...

Description This role involves the comprehensive bench-level validation, bring-up, and characterization of DDR memory interfaces within Apple's cutting-edge SoCs. You will be responsible for ...

... DDR/Memory, Security/Boot, Low-Speed IO, and other critical technologies - that customers and internal SoC teams can adopt with confidence. By shifting left, the COE enables faster time-to-market ...

Description This role involves the comprehensive bench-level validation, bring-up, and characterization of DDR memory interfaces within Apple's cutting-edge SoCs. You will be responsible for ...

Description This role involves the comprehensive bench-level validation, bring-up, and characterization of DDR memory interfaces within Apple's cutting-edge SoCs. You will be responsible for ...

Description This role involves the comprehensive bench-level validation, bring-up, and characterization of DDR memory interfaces within Apple's cutting-edge SoCs. You will be responsible for ...

Own DDR5 and LPDDR5 memory subsystem validation, including defining and executing validation strategies across multiple FPGA programs. * Create, define, and develop comprehensive system-level ...