Ddr Memory Jobs in California (NOW HIRING)

Post -Silicon Engineer - DDR Memory Location: Sunnyvale, CA JD: * HBM / DDR expert * Experience in memory validation * Understanding of memory training and understanding of memory test algorithms

Responsibilities * Serve as the technical lead for Design Verification of complex DDR memory subsystems across multiple FPGA product families. * Define and drive verification architecture ...

Responsibilities * Serve as the technical lead for Design Verification of complex DDR memory subsystems across multiple FPGA product families. * Define and drive verification architecture ...

Architect high-performance HBM/DDR memory subsystems for Marvell's custom compute products, including developing specifications, performance models, and product requirements. * Define and evolve ...

Architect high-performance HBM/DDR memory subsystems for Marvell's custom compute products, including developing specifications, performance models, and product requirements. * Define and evolve ...

Architect high-performance HBM/DDR memory subsystems for Marvell's custom compute products, including developing specifications, performance models, and product requirements. * Define and evolve ...

Description This role involves the comprehensive bench-level validation, bring-up, and characterization of DDR memory interfaces within Apple's cutting-edge SoCs. You will be responsible for ...

Description This role involves the comprehensive bench-level validation, bring-up, and characterization of DDR memory interfaces within Apple's cutting-edge SoCs. You will be responsible for ...

Description This role involves the comprehensive bench-level validation, bring-up, and characterization of DDR memory interfaces within Apple's cutting-edge SoCs. You will be responsible for ...

... DDR/Memory, Security/Boot, Low-Speed IO, and other critical technologies - that customers and internal SoC teams can adopt with confidence. By shifting left, the COE enables faster time-to-market ...

... DDR/Memory, Security/Boot, Low-Speed IO, and other critical technologies - that customers and internal SoC teams can adopt with confidence. By shifting left, the COE enables faster time-to-market ...

Description This role involves the comprehensive bench-level validation, bring-up, and characterization of DDR memory interfaces within Apple's cutting-edge SoCs. You will be responsible for ...

Experience with BIOS, firmware, DDR memory, or lab bench testing is preferable. Salary Range: * $100,000-155,000+ depending on experience and location. Weekly Schedule: * Hybrid schedule (3 days ...

Design systems utilizing high-speed DDR memory controllers and high-speed serial transceivers. * Develop designs that achieve timing closure, including handling clock domain crossings. * Support ...

Planning and performing DDR memory tuning, validation, and feature enablement on NVIDIA products. * Reviewing silicon design specifications, component datasheets, board schematics, and layout.

Own DDR5 and LPDDR5 memory subsystem validation, including defining and executing validation strategies across multiple FPGA programs. * Create, define, and develop comprehensive system-level ...

Planning and performing DDR memory tuning, validation, and feature enablement on NVIDIA products. * Reviewing silicon design specifications, component datasheets, board schematics, and layout.

Own DDR5 and LPDDR5 memory subsystem validation, including defining and executing validation strategies across multiple FPGA programs. * Create, define, and develop comprehensive system-level ...

Develop and execute verification plans for high-speed memory interfaces (DDR4/DDR5, LPDDR4/LPDDR5 ... Strong knowledge of DDR, LPDDR, or HBM protocols and architecture * Expertise in System Verilog and ...

Develop and execute verification plans for high-speed memory interfaces (DDR4/DDR5, LPDDR4/LPDDR5 ... Strong knowledge of DDR, LPDDR, or HBM protocols and architecture * Expertise in System Verilog and ...