The Principal Engineer will serve as the technical leader for the IO subsystem, driving architecture, RTL implementation, and design automation strategy, while partnering closely with system ...
The Principal Engineer will serve as the technical leader for the IO subsystem, driving architecture, RTL implementation, and design automation strategy, while partnering closely with system ...
Drive RTL development and verification (RTL and Gate level) * Develop timing constraints and ... Design Engineer, including 3 years of design verification of mixed signal developments.
Drive RTL development and verification (RTL and Gate level) * Develop timing constraints and ... Design Engineer, including 3 years of design verification of mixed signal developments.
Digital IC Design Engineer - USB Products
Dallas, TX · On-site
$123K/yr
Responsibilities include RTL design, design verification, and DFT, and being a technical ... As a design engineer, you will prepare test methods and specifications, assist in preparation of ...
Digital IC Design Engineer - USB Products
Dallas, TX · On-site
$123K/yr
Responsibilities include RTL design, design verification, and DFT, and being a technical ... As a design engineer, you will prepare test methods and specifications, assist in preparation of ...
The Principal Engineer will serve as the technical leader for the IO subsystem, driving architecture, RTL implementation, and design automation strategy, while partnering closely with system ...
The Principal Engineer will serve as the technical leader for the IO subsystem, driving architecture, RTL implementation, and design automation strategy, while partnering closely with system ...
The Principal Engineer will serve as the technical leader for the IO subsystem, driving architecture, RTL implementation, and design automation strategy, while partnering closely with system ...
The Principal Engineer will serve as the technical leader for the IO subsystem, driving architecture, RTL implementation, and design automation strategy, while partnering closely with system ...
Experience in RTL design and design verification, preferred * Ability to create and present design reviews, test/characterization plans * Programming skills highly desirable, e.g. PERL, Python, SKIL ...
Experience in RTL design and design verification, preferred * Ability to create and present design reviews, test/characterization plans * Programming skills highly desirable, e.g. PERL, Python, SKIL ...
Design Verification Engineer
Plano, TX · On-site
$130K - $158K/yr
You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a ...
Quick apply
Design Verification Engineer
Plano, TX · On-site
$130K - $158K/yr
You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a ...
Over 4 years working in custom design verification (schematic‑based) or RTL design verification ... Master's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent ...
Over 4 years working in custom design verification (schematic‑based) or RTL design verification ... Master's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent ...
Senior Staff Digital Design Engineer Plano, Texas, United States Sense the power of light ams OSRAM ... Translate customer and system requirements into optimized RTL architectures and high-quality ...
Senior Staff Digital Design Engineer Plano, Texas, United States Sense the power of light ams OSRAM ... Translate customer and system requirements into optimized RTL architectures and high-quality ...
Staff Wireless IC Digital Designer
Dallas, TX · On-site
$134K/yr
Staff Wireless Digital Design Engineer About the Role As a Senior Staff Wireless IC Digital ... Perform RTL design of block-level IP. * Perform RTL design and integration of RFIC architectures.
Staff Wireless IC Digital Designer
Dallas, TX · On-site
$134K/yr
Staff Wireless Digital Design Engineer About the Role As a Senior Staff Wireless IC Digital ... Perform RTL design of block-level IP. * Perform RTL design and integration of RFIC architectures.
As a Design Engineer at Micron Technology, Inc., you will be responsible for designing and ... Prior register‑transfer level (RTL) design flow experience in DRAM or foundry processes.
As a Design Engineer at Micron Technology, Inc., you will be responsible for designing and ... Prior register‑transfer level (RTL) design flow experience in DRAM or foundry processes.
About the Role We're looking for a talented Digital Design Engineer to join our team, where you'll ... Write and review RTL code , and drive designs through simulation, synthesis, and timing closure
About the Role We're looking for a talented Digital Design Engineer to join our team, where you'll ... Write and review RTL code , and drive designs through simulation, synthesis, and timing closure
HBM SOC Design Engineer
Richardson, TX · On-site
As an HBM SOC Design Engineer, you will be responsible for the design & development of next ... You will apply your deep understanding of SOC Architecture, RTL Logic Design, IP Integration, high ...
HBM SOC Design Engineer
Richardson, TX · On-site
As an HBM SOC Design Engineer, you will be responsible for the design & development of next ... You will apply your deep understanding of SOC Architecture, RTL Logic Design, IP Integration, high ...
You will work closely with RTL design, physical design, architecture, DFT, verification, and ... Mentor and grow junior engineers, contribute to design documentation and timing sign‑off ...
You will work closely with RTL design, physical design, architecture, DFT, verification, and ... Mentor and grow junior engineers, contribute to design documentation and timing sign‑off ...
Digital IC Design Engineer (INT TRX)
Dallas, TX · On-site
$123K/yr
About the Role We're looking for a talented Digital Design Engineer to join our team, where you'll ... Write and review RTL code , and drive designs through simulation, synthesis, and timing closure
Digital IC Design Engineer (INT TRX)
Dallas, TX · On-site
$123K/yr
About the Role We're looking for a talented Digital Design Engineer to join our team, where you'll ... Write and review RTL code , and drive designs through simulation, synthesis, and timing closure
HBM SOC Design Engineer
Richardson, TX · On-site
As an HBM SOC Design Engineer, you will be responsible for the design & development of next ... You will apply your deep understanding of SOC Architecture, RTL Logic Design, IP Integration, high ...
HBM SOC Design Engineer
Richardson, TX · On-site
As an HBM SOC Design Engineer, you will be responsible for the design & development of next ... You will apply your deep understanding of SOC Architecture, RTL Logic Design, IP Integration, high ...
Digital IC Design Engineer
Dallas, TX · On-site
$123K/yr
Drive the full digital flow from RTL to physical layout (RTL-to-GDSII), applying and advancing ... Partner with Design Verification, Validation, Product Engineering, and Test Engineering to ensure a ...
Digital IC Design Engineer
Dallas, TX · On-site
$123K/yr
Drive the full digital flow from RTL to physical layout (RTL-to-GDSII), applying and advancing ... Partner with Design Verification, Validation, Product Engineering, and Test Engineering to ensure a ...
HBM SoC Physical Design Engineer
Richardson, TX · On-site
$123K - $127K/yr
As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the ... You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and ...
HBM SoC Physical Design Engineer
Richardson, TX · On-site
$123K - $127K/yr
As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the ... You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and ...
HBM SoC Physical Design Engineer
Richardson, TX · On-site
$123K - $127K/yr
As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the ... You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and ...
HBM SoC Physical Design Engineer
Richardson, TX · On-site
$123K - $127K/yr
As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the ... You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and ...
HBM SoC Physical Design Engineer
Richardson, TX · On-site
$123K - $127K/yr
As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the ... You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and ...
HBM SoC Physical Design Engineer
Richardson, TX · On-site
$123K - $127K/yr
As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the ... You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and ...
Cpu Rtl Design Engineer information
See Plano, TX salary details
$38.8K - $49K
2% of jobs
$49K - $59.3K
11% of jobs
$64.8K is the 25th percentile. Wages below this are outliers.
$59.3K - $69.6K
23% of jobs
The median wage is $76.2K / yr.
$69.6K - $79.8K
22% of jobs
$79.8K - $90.1K
17% of jobs
$90.4K is the 75th percentile. Wages above this are outliers.
$90.1K - $100.4K
9% of jobs
$100.4K - $110.6K
6% of jobs
$110.6K - $120.9K
3% of jobs
$120.9K - $131.2K
3% of jobs
$131.2K - $141.4K
2% of jobs
$141.4K - $151.7K
1% of jobs
$38.8K
$84.4K
$151.7K
How much do cpu rtl design engineer jobs pay per year?
What is a CPU RTL design engineer?
What are the key skills and qualifications needed to thrive as a CPU RTL design engineer?
What are some common challenges faced by CPU RTL design engineers when collaborating with verification and architecture teams?
What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?
| Aspect | Cpu Rtl Design Engineer | Cpu Verification Engineer |
|---|---|---|
| Primary Focus | Designing and developing RTL code for CPU components | Verifying and testing RTL designs for correctness |
| Skills & Certifications | HDL languages (Verilog/VHDL), FPGA/ASIC design experience | HDL, testbench development, simulation tools |
| Work Environment | Design teams, hardware development labs | Verification teams, simulation environments |
| Industry Usage | Semiconductor companies, CPU design firms | ASIC/FPGA verification, chip validation |
While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.
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Cities near Plano, TX with the most Cpu Rtl Design Engineer job openings:
Principal Engineer, Digital Design (IO Subsystem)
Allen, TX • On-site
Other
Re-posted 22 days ago
Onsemi rating
8.3
Based on 20 frontline employees who took The Breakroom Quiz
Job description
We are seeking a Principal Digital Design Engineer based in Allen, TX, to own the IO subsystem for onsemi’s microcontroller platform. In this role, you will be responsible for defining, architecting, and delivering a highly configurable IO subsystem that supports a wide range of product requirements across multiple end markets.
This position plays a critical role in enabling platform scalability and product differentiation. The IO subsystem must be flexible, reusable, and optimized for performance, power, and area while supporting a wide range of product requirements.
The Principal Engineer will serve as the technical leader for the IO subsystem, driving architecture, RTL implementation, and design automation strategy, while partnering closely with system architecture, product lines, DFT, physical design, verification, and software teams. This role requires strong technical execution, cross‑functional leadership, and the ability to influence platform direction.
Responsibilities- Own the architecture and development of the IO subsystem, ensuring configurability and reuse across multiple products
- Define subsystem‑level specifications, interfaces, and integration strategy aligned with platform and product requirements
- Define and implement parameterized and Python generator‑based design approaches, enabling scalable and configurable subsystem instantiation
- Drive the creation of automatically generated testbenches and verification environments, leveraging UVM frameworks and AI‑assisted techniques
- Develop high‑quality SystemVerilog RTL, ensuring compatibility with automated generation flows and maintainability at scale
- Support synthesis, STA, and timing closure activities to ensure signoff‑ready designs
- Collaborate with verification, DFT, and physical design teams to achieve first‑time right silicon
- Apply AI/ML techniques to improve design productivity, including code generation assistance, verification acceleration, and design space exploration
- Drive PPA optimization while maintaining configurability and reuse targets
- Establish best practices for design automation, code generation, and methodology standardization across the organization
Required
- Bachelor’s degree in Electrical Engineering or related field (Master’s preferred)
- 10+ years of experience in digital IC design with strong RTL development background
- Expert‑level proficiency in SystemVerilog RTL design
- Strong experience with Python for design automation and tool development
- Solid experience with UVM‑based verification methodologies and testbench development
- Strong understanding of UPF, synthesis, STA, and timing signoff flows
- Experience working with DFT concepts and integration
- Strong cross‑functional collaboration skills across design, verification, physical design, and product teams
Preferred
- Experience designing IO subsystems or peripheral architectures for microcontrollers or SoCs
- Experience with design generators, templated RTL, or hardware construction frameworks
- Exposure to AI/ML techniques applied to hardware design or verification workflows
- Experience building or deploying automated testbench generation and regression systems
- Familiarity with highly configurable or parameterized architectures
- Experience in automotive or safety‑critical designs
onsemi is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, ethnicity, color, religion, ancestry, national origin, age, marital status, pregnancy, sex, sexual orientation, physical or mental disability, medical condition, genetic information, military or veteran status, gender identity, gender expression, or any other protected category under applicable federal, state, or local laws. If you are an individual with a disability and require a reasonable accommodation to complete any part of the application process, or are limited in the ability or unable to access or use this online application process and need an alternative method for applying, you may contact Talent.acquisition@onsemi.com for assistance.
Job Info- Job Identification 2505665
- Job Category Engineering, Design
- Posting Date 06/19/2026, 01:11 AM
- Degree Level Bachelors
- Job Schedule Full time
- Job Shift Day
About onsemi
Sourced by ZipRecruiter
Industry
Electrical equipment, appliance, and component manufacturing
Company size
10,000+ Employees
Headquarters location
Phoenix, AZ, US