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Cpu Rtl Design Engineer Jobs in Plano, TX (NOW HIRING)

The Principal Engineer will serve as the technical leader for the IO subsystem, driving architecture, RTL implementation, and design automation strategy, while partnering closely with system ...

Design Verification Engineer

Plano, TX · On-site

$130K - $158K/yr

You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a ...

Senior Staff Digital Design Engineer Plano, Texas, United States Sense the power of light ams OSRAM ... Translate customer and system requirements into optimized RTL architectures and high-quality ...

As an HBM SOC Design Engineer, you will be responsible for the design & development of next ... You will apply your deep understanding of SOC Architecture, RTL Logic Design, IP Integration, high ...

Digital IC Design Engineer

Dallas, TX · On-site

$123K/yr

Drive the full digital flow from RTL to physical layout (RTL-to-GDSII), applying and advancing ... Partner with Design Verification, Validation, Product Engineering, and Test Engineering to ensure a ...

HBM SoC Physical Design Engineer

Richardson, TX · On-site

$123K - $127K/yr

As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the ... You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and ...

HBM SoC Physical Design Engineer

Richardson, TX · On-site

$123K - $127K/yr

As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the ... You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and ...

Showing results 21-40

Cpu Rtl Design Engineer information

See Plano, TX salary details

$38.8K

$84.4K

$151.7K

How much do cpu rtl design engineer jobs pay per year?

As of Sep 9, 2026, the average yearly pay for cpu rtl design engineer in Plano, TX is $84,367.00, according to ZipRecruiter salary data. Most workers in this role earn between $65,100.00 and $94,300.00 per year, depending on experience, location, and employer.

What is a CPU RTL design engineer?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.

What are the key skills and qualifications needed to thrive as a CPU RTL design engineer?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What are some common challenges faced by CPU RTL design engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What are popular job titles related to Cpu Rtl Design Engineer jobs in Plano, TX?

For Cpu Rtl Design Engineer jobs in Plano, TX, the most frequently searched job titles are:

What job categories do people searching Cpu Rtl Design Engineer jobs in Plano, TX look for?

The top searched job categories for Cpu Rtl Design Engineer jobs in Plano, TX are:

What cities near Plano, TX are hiring for Cpu Rtl Design Engineer jobs?

Cities near Plano, TX with the most Cpu Rtl Design Engineer job openings:

Principal Engineer, Digital Design (IO Subsystem)

Allen, TX • On-site

onsemi
Electrical Equipment, Appliance, and Component Manufacturing • 10K+ employees

Other

Re-posted 22 days ago


Onsemi rating

8.3

Company rating: 8.3 out of 10

Based on 20 frontline employees who took The Breakroom Quiz


Job description

Principal Engineer, Digital Design (IO Subsystem) Job Description

We are seeking a Principal Digital Design Engineer based in Allen, TX, to own the IO subsystem for onsemi’s microcontroller platform. In this role, you will be responsible for defining, architecting, and delivering a highly configurable IO subsystem that supports a wide range of product requirements across multiple end markets.

This position plays a critical role in enabling platform scalability and product differentiation. The IO subsystem must be flexible, reusable, and optimized for performance, power, and area while supporting a wide range of product requirements.

The Principal Engineer will serve as the technical leader for the IO subsystem, driving architecture, RTL implementation, and design automation strategy, while partnering closely with system architecture, product lines, DFT, physical design, verification, and software teams. This role requires strong technical execution, cross‑functional leadership, and the ability to influence platform direction.

Responsibilities
  • Own the architecture and development of the IO subsystem, ensuring configurability and reuse across multiple products
  • Define subsystem‑level specifications, interfaces, and integration strategy aligned with platform and product requirements
  • Define and implement parameterized and Python generator‑based design approaches, enabling scalable and configurable subsystem instantiation
  • Drive the creation of automatically generated testbenches and verification environments, leveraging UVM frameworks and AI‑assisted techniques
  • Develop high‑quality SystemVerilog RTL, ensuring compatibility with automated generation flows and maintainability at scale
  • Support synthesis, STA, and timing closure activities to ensure signoff‑ready designs
  • Collaborate with verification, DFT, and physical design teams to achieve first‑time right silicon
  • Apply AI/ML techniques to improve design productivity, including code generation assistance, verification acceleration, and design space exploration
  • Drive PPA optimization while maintaining configurability and reuse targets
  • Establish best practices for design automation, code generation, and methodology standardization across the organization
Qualifications

Required

  • Bachelor’s degree in Electrical Engineering or related field (Master’s preferred)
  • 10+ years of experience in digital IC design with strong RTL development background
  • Expert‑level proficiency in SystemVerilog RTL design
  • Strong experience with Python for design automation and tool development
  • Solid experience with UVM‑based verification methodologies and testbench development
  • Strong understanding of UPF, synthesis, STA, and timing signoff flows
  • Experience working with DFT concepts and integration
  • Strong cross‑functional collaboration skills across design, verification, physical design, and product teams

Preferred

  • Experience designing IO subsystems or peripheral architectures for microcontrollers or SoCs
  • Experience with design generators, templated RTL, or hardware construction frameworks
  • Exposure to AI/ML techniques applied to hardware design or verification workflows
  • Experience building or deploying automated testbench generation and regression systems
  • Familiarity with highly configurable or parameterized architectures
  • Experience in automotive or safety‑critical designs

onsemi is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, ethnicity, color, religion, ancestry, national origin, age, marital status, pregnancy, sex, sexual orientation, physical or mental disability, medical condition, genetic information, military or veteran status, gender identity, gender expression, or any other protected category under applicable federal, state, or local laws. If you are an individual with a disability and require a reasonable accommodation to complete any part of the application process, or are limited in the ability or unable to access or use this online application process and need an alternative method for applying, you may contact Talent.acquisition@onsemi.com for assistance.

Job Info
  • Job Identification 2505665
  • Job Category Engineering, Design
  • Posting Date 06/19/2026, 01:11 AM
  • Degree Level Bachelors
  • Job Schedule Full time
  • Job Shift Day
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