Digital Signal Processing/Forward Error Correction Engineer, Linthicum Heights, MD We are looking ... Preferred Qualifications: - Familiarity with FPGA and RTL design including hardware description ...
Digital Signal Processing/Forward Error Correction Engineer, Linthicum Heights, MD We are looking ... Preferred Qualifications: - Familiarity with FPGA and RTL design including hardware description ...
ASIC Digital Design Engineer
Annapolis Junction, MD · On-site +1
$114K - $120K/yr
Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other languages. * Integrate ... Contribute to all aspects of design success from specification to production. * Apply our ...
ASIC Digital Design Engineer
Annapolis Junction, MD · On-site +1
$114K - $120K/yr
Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other languages. * Integrate ... Contribute to all aspects of design success from specification to production. * Apply our ...
Senior Hardware/ Software Design Engineer (HSDE3) with Security Clearance
Annapolis Junction, MD · On-site
Seeking an experienced senior HW/SW Design Engineer to join a small team to design, develop ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
Senior Hardware/ Software Design Engineer (HSDE3) with Security Clearance
Annapolis Junction, MD · On-site
Seeking an experienced senior HW/SW Design Engineer to join a small team to design, develop ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
Hoplite Solutions is seeking an experienced senior HW/SW Design Engineer to join a small team to ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
Hoplite Solutions is seeking an experienced senior HW/SW Design Engineer to join a small team to ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
Principal FPGA Architect -- DoD Systems Lead
Ashburn, VA · On-site
$144.10 - $192.10/hr
... Engineer to join our team in Ashburn, VA. In this senior role, you will lead the design and ... flows including RTL design. This is an onsite position that offers a competitive salary and ...
Principal FPGA Architect -- DoD Systems Lead
Ashburn, VA · On-site
$144.10 - $192.10/hr
... Engineer to join our team in Ashburn, VA. In this senior role, you will lead the design and ... flows including RTL design. This is an onsite position that offers a competitive salary and ...
Que Technology Group, Inc., is seeking an experienced senior hardware/software design engineer to ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
Que Technology Group, Inc., is seeking an experienced senior hardware/software design engineer to ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
Que Technology Group, Inc., is seeking an experienced senior hardware/software design engineer to ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
Quick apply
Que Technology Group, Inc., is seeking an experienced senior hardware/software design engineer to ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
Senior FPGA Electrical Engineer
Linthicum, MD · On-site
$102K - $138K/yr
Senior FPGA Electrical Engineer, Linthicum Heights, MD We are looking for multiple Senior FPGA ... partition design within ASIC/FPGA, create specification documents. - Develop RTL designs using ...
Senior FPGA Electrical Engineer
Linthicum, MD · On-site
$102K - $138K/yr
Senior FPGA Electrical Engineer, Linthicum Heights, MD We are looking for multiple Senior FPGA ... partition design within ASIC/FPGA, create specification documents. - Develop RTL designs using ...
Senior FPGA Engineer
Fairfax, VA · On-site
$97 - $181/hr
Senior FPGA Engineer Requisition ID: 1806 Position Location: Fairfax, VA Position Reports To ... The ideal candidate brings deep expertise in RTL design, timing closure, simulation, and system ...
Senior FPGA Engineer
Fairfax, VA · On-site
$97 - $181/hr
Senior FPGA Engineer Requisition ID: 1806 Position Location: Fairfax, VA Position Reports To ... The ideal candidate brings deep expertise in RTL design, timing closure, simulation, and system ...
Senior FPGA Engineer
Fairfax, VA · On-site
$97K - $181K/yr
Senior FPGA Engineer Requisition ID: 1806 Position Location: Fairfax, VA Position Reports To ... The ideal candidate brings deep expertise in RTL design, timing closure, simulation, and system ...
Quick apply
Senior FPGA Engineer
Fairfax, VA · On-site
$97K - $181K/yr
Senior FPGA Engineer Requisition ID: 1806 Position Location: Fairfax, VA Position Reports To ... The ideal candidate brings deep expertise in RTL design, timing closure, simulation, and system ...
Own RTL design, simulation, verification, and lab bring-up across VHDL, Verilog, or SystemVerilog-based workflows. * Work closely with DSP, software, hardware, and systems engineers to turn algorithm ...
Own RTL design, simulation, verification, and lab bring-up across VHDL, Verilog, or SystemVerilog-based workflows. * Work closely with DSP, software, hardware, and systems engineers to turn algorithm ...
The engineer will lead technical design efforts, implement DSP algorithms and associated technical ... What you will do This role combines hardware design responsibilities (FPGA RTL development, timing ...
The engineer will lead technical design efforts, implement DSP algorithms and associated technical ... What you will do This role combines hardware design responsibilities (FPGA RTL development, timing ...
FPGA Engineer
Linthicum, MD · On-site
$128K - $164K/yr
... design within ASIC/FPGA, create specification documents. - Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer ...
FPGA Engineer
Linthicum, MD · On-site
$128K - $164K/yr
... design within ASIC/FPGA, create specification documents. - Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer ...
388 Senior Hardware/Software Design Engineer with Security Clearance
Annapolis Junction, MD · On-site
$167K - $187K/yr
388 Senior Hardware/Software Design Engineer Annapolis Junction, MD Hardware/Software Design ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
388 Senior Hardware/Software Design Engineer with Security Clearance
Annapolis Junction, MD · On-site
$167K - $187K/yr
388 Senior Hardware/Software Design Engineer Annapolis Junction, MD Hardware/Software Design ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
Engineer
Fairfax, VA · On-site
... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...
Engineer
Fairfax, VA · On-site
... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...
Engineer
Fairfax, VA · On-site
... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...
Engineer
Fairfax, VA · On-site
... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...
Electrical Engineer - FPGA, EO/IR Sensors, Embedded Systems & Signal Processing Location ... RTL, and embedded software. • Design and support PCB development using Altium Designer. • ...
Electrical Engineer - FPGA, EO/IR Sensors, Embedded Systems & Signal Processing Location ... RTL, and embedded software. • Design and support PCB development using Altium Designer. • ...
Senior FPGA Engineer
Linthicum, MD · On-site
$128K - $164K/yr
Senior FPGA Engineer, Linthicum Heights, MD We are looking for multiple candidates at multiple ... partition design within ASIC/FPGA, create specification documents. - Develop RTL designs using ...
Senior FPGA Engineer
Linthicum, MD · On-site
$128K - $164K/yr
Senior FPGA Engineer, Linthicum Heights, MD We are looking for multiple candidates at multiple ... partition design within ASIC/FPGA, create specification documents. - Develop RTL designs using ...
Amentum Seeking an experienced senior HW/SW Design Engineer to join a small team to design, develop ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
Amentum Seeking an experienced senior HW/SW Design Engineer to join a small team to design, develop ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
Amentum Seeking an experienced senior HW/SW Design Engineer to join a small team to design, develop ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
Amentum Seeking an experienced senior HW/SW Design Engineer to join a small team to design, develop ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
Cpu Rtl Design Engineer information
See Washington salary details
$45.9K - $58K
2% of jobs
$58K - $70.2K
11% of jobs
$76.7K is the 25th percentile. Wages below this are outliers.
$70.2K - $82.3K
23% of jobs
The median wage is $90.1K / yr.
$82.3K - $94.5K
22% of jobs
$94.5K - $106.6K
17% of jobs
$107K is the 75th percentile. Wages above this are outliers.
$106.6K - $118.8K
9% of jobs
$118.8K - $130.9K
6% of jobs
$130.9K - $143.1K
3% of jobs
$143.1K - $155.2K
3% of jobs
$155.2K - $167.4K
2% of jobs
$167.4K - $179.5K
1% of jobs
$45.9K
$99.8K
$179.5K
How much do cpu rtl design engineer jobs pay per year?
As of Aug 11, 2026, the average yearly pay for cpu rtl design engineer in Washington is $99,838.00, according to ZipRecruiter salary data. Most workers in this role earn between $77,000.00 and $111,600.00 per year, depending on experience, location, and employer.
What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?
| Aspect | Cpu Rtl Design Engineer | Cpu Verification Engineer |
|---|---|---|
| Primary Focus | Designing and developing RTL code for CPU components | Verifying and testing RTL designs for correctness |
| Skills & Certifications | HDL languages (Verilog/VHDL), FPGA/ASIC design experience | HDL, testbench development, simulation tools |
| Work Environment | Design teams, hardware development labs | Verification teams, simulation environments |
| Industry Usage | Semiconductor companies, CPU design firms | ASIC/FPGA verification, chip validation |
While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.
What are some common challenges faced by CPU RTL design engineers when collaborating with verification and architecture teams?
CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.
What are the key skills and qualifications needed to thrive as a CPU RTL design engineer?
To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.
What is a CPU RTL design engineer?
CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.
What are popular job titles related to Cpu Rtl Design Engineer jobs in Washington? For Cpu Rtl Design Engineer jobs in Washington, the most frequently searched job titles are:
What job categories do people searching Cpu Rtl Design Engineer jobs in Washington look for? The top searched job categories for Cpu Rtl Design Engineer jobs in Washington are:
What cities in Washington are hiring for Cpu Rtl Design Engineer jobs? Cities in Washington with the most Cpu Rtl Design Engineer job openings:
Full-time
Medical, Retirement, PTO
Re-posted 5 days ago
Job description
Digital Signal Processing/Forward Error Correction Engineer, Linthicum Heights, MD
We are looking for multiple candidates at multiple levels for this Digital Signal Processing/Forward Error Correction Engineer position. Candidates must be US Citizens and cannot have Dual Citizenships. All candidates must be fully vaccinated with an FDA authorized and/or approved COVID-19 vaccine as a condition of employment. Requests for reasonable accommodations for medical, religious, or other reasons will be considered in accordance with applicable law. These positions are 100% Onsite.
Responsibilities:
- Familiarity with standard classes of codes, including BCH, Reed-Solomon, Reed-Muller, Golay Codes, Convolutional Codes, Turbo Codes, LDPCs, Polar Codes, etc.
- Ability to analyze systems and communication channels and choose modulation and coding (including code design, rates, puncturing schemes, etc) that are most appropriate to maximize performance.
- Contribute to algorithm design, analysis and architecture specification for DSP blocks of a digital front end various radio architectures.
- Derive requirements, conceptualize, define, design & prototype systems engineering solutions.
- Understand system-level requirements and work with various teams to ensure that designs and implementations are meeting expectations.
- Document designs and interfaces, distribute across teams and conduct reviews and discussions.
- Understand the big picture but also break down to system-level components to capture dependencies, bottlenecks or risk areas in design.
- Work with systems architects and hardware engineers to develop, implement and test robust radio signal processing algorithms.
- Test, verification and debug of field test systems.
Minimum Qualifications:
- Knowledge of modulation, demodulation, forward error correction, randomization, and packet analysis.
- Prior experience designing and/or building wireless communications transmitters and receivers.
- Familiar with design, optimization and testing of communication signal processing algorithms.
- Experience in writing Matlab and C/C++ to emulate system test conditions.
- Understanding of commercial standards (e.g., 802.11, 4G/5G, etc.).
- Proficient in Matlab, Mathematica, Python or other scripting language, simulation tools.
- Proficient in creating engineering documents: system designs, interface specifications, requirements/specifications, etc.
Preferred Qualifications:
- Familiarity with FPGA and RTL design including hardware description languages (Verilog, System Verilog, VHDL).
- Good knowledge and understanding across various engineering principles that apply to wireless communications systems (RF, DSP, FPGA, software, digital/hardware, mechanical/packaging) and their interdependencies.
- Experience designing RF front-end architectures.
Benefits include medical insurance, retirement plan, PTO, etc. Salary: 80K+ DOE. Keywords: Linthicum Heights MD Jobs, Digital Signal Processing/Forward Error Correction Engineer, Matlab, C/C++, Mathematica, Python, FPGA, RTL Design, Verilog, System Verilog, VHDL, RF, DSP, Software, Digital Hardware, Engineering, Maryland Recruiters, Information Technology Jobs, IT Jobs, Maryland Recruiting
Looking to hire for similar positions in Linthicum Heights, MD or in other cities? Our IT recruiting agencies and staffing companies can help.
We help companies that are looking to hire Digital Signal Processing/Forward Error Correction Engineers for jobs in Linthicum Heights, Maryland and in other cities too. Please contact our IT recruiting agencies and IT staffing companies today! Phone 630-428-0600 ext. 11 or email us at jobs@nextstepsystems.com. Click here to submit your resume for this job and others.
Atlanta, Austin, Baltimore, Boston, Charlotte, Chicago, Cincinnati, Cleveland, Columbus, Dallas, Denver, Detroit, Fort Lauderdale, Houston, Indianapolis, Jacksonville, Kansas City, Los Angeles, Miami, Minneapolis, Nashville, New Jersey, New York, Philadelphia, Phoenix, Raleigh, Salt Lake City, San Antonio, San Diego, San Francisco, San Jose, Seattle, Silicon Valley, St Louis, Tampa, Washington DC
We are looking for multiple candidates at multiple levels for this Digital Signal Processing/Forward Error Correction Engineer position. Candidates must be US Citizens and cannot have Dual Citizenships. All candidates must be fully vaccinated with an FDA authorized and/or approved COVID-19 vaccine as a condition of employment. Requests for reasonable accommodations for medical, religious, or other reasons will be considered in accordance with applicable law. These positions are 100% Onsite.
Responsibilities:
- Familiarity with standard classes of codes, including BCH, Reed-Solomon, Reed-Muller, Golay Codes, Convolutional Codes, Turbo Codes, LDPCs, Polar Codes, etc.
- Ability to analyze systems and communication channels and choose modulation and coding (including code design, rates, puncturing schemes, etc) that are most appropriate to maximize performance.
- Contribute to algorithm design, analysis and architecture specification for DSP blocks of a digital front end various radio architectures.
- Derive requirements, conceptualize, define, design & prototype systems engineering solutions.
- Understand system-level requirements and work with various teams to ensure that designs and implementations are meeting expectations.
- Document designs and interfaces, distribute across teams and conduct reviews and discussions.
- Understand the big picture but also break down to system-level components to capture dependencies, bottlenecks or risk areas in design.
- Work with systems architects and hardware engineers to develop, implement and test robust radio signal processing algorithms.
- Test, verification and debug of field test systems.
Minimum Qualifications:
- Knowledge of modulation, demodulation, forward error correction, randomization, and packet analysis.
- Prior experience designing and/or building wireless communications transmitters and receivers.
- Familiar with design, optimization and testing of communication signal processing algorithms.
- Experience in writing Matlab and C/C++ to emulate system test conditions.
- Understanding of commercial standards (e.g., 802.11, 4G/5G, etc.).
- Proficient in Matlab, Mathematica, Python or other scripting language, simulation tools.
- Proficient in creating engineering documents: system designs, interface specifications, requirements/specifications, etc.
Preferred Qualifications:
- Familiarity with FPGA and RTL design including hardware description languages (Verilog, System Verilog, VHDL).
- Good knowledge and understanding across various engineering principles that apply to wireless communications systems (RF, DSP, FPGA, software, digital/hardware, mechanical/packaging) and their interdependencies.
- Experience designing RF front-end architectures.
Benefits include medical insurance, retirement plan, PTO, etc. Salary: 80K+ DOE. Keywords: Linthicum Heights MD Jobs, Digital Signal Processing/Forward Error Correction Engineer, Matlab, C/C++, Mathematica, Python, FPGA, RTL Design, Verilog, System Verilog, VHDL, RF, DSP, Software, Digital Hardware, Engineering, Maryland Recruiters, Information Technology Jobs, IT Jobs, Maryland Recruiting
Looking to hire for similar positions in Linthicum Heights, MD or in other cities? Our IT recruiting agencies and staffing companies can help.
We help companies that are looking to hire Digital Signal Processing/Forward Error Correction Engineers for jobs in Linthicum Heights, Maryland and in other cities too. Please contact our IT recruiting agencies and IT staffing companies today! Phone 630-428-0600 ext. 11 or email us at jobs@nextstepsystems.com. Click here to submit your resume for this job and others.
Atlanta, Austin, Baltimore, Boston, Charlotte, Chicago, Cincinnati, Cleveland, Columbus, Dallas, Denver, Detroit, Fort Lauderdale, Houston, Indianapolis, Jacksonville, Kansas City, Los Angeles, Miami, Minneapolis, Nashville, New Jersey, New York, Philadelphia, Phoenix, Raleigh, Salt Lake City, San Antonio, San Diego, San Francisco, San Jose, Seattle, Silicon Valley, St Louis, Tampa, Washington DC
About Next Step Systems
Sourced by ZipRecruiter
Industry
It services
Company size
11 - 50 Employees
Headquarters location
Naperville, IL, US
Year founded
1995