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Contractual Silicon Foundry Interface Engineer Jobs

Lightmatter

Foundry Engineer

Mountain View, CA · On-site

The team will be creating product-specific silicon manufacturing process flow plan, working with ... Experience in foundry manufacturing process or process development/integration engineer in any fab ...

Lightmatter

Foundry Engineer

Mountain View, CA · On-site

$180K - $212K/yr

The team will be creating product-specific silicon manufacturing process flow plan, working with ... Experience in foundry manufacturing process or process development/integration engineer in any fab ...

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Contractual Silicon Foundry Interface Engineer information

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$60K

$80.4K

$111.5K

How much do contractual silicon foundry interface engineer jobs pay per year?

As of Jul 26, 2026, the average yearly pay for contractual silicon foundry interface engineer in the United States is $80,416.00, according to ZipRecruiter salary data. Most workers in this role earn between $70,500.00 and $85,000.00 per year, depending on experience, location, and employer.

What are the typical challenges a Contractual Silicon Foundry Interface Engineer faces when coordinating between design teams and foundry partners?

A Contractual Silicon Foundry Interface Engineer often encounters challenges related to aligning the technical requirements and timelines of internal design teams with the manufacturing processes and capabilities of external foundry partners. Communication gaps can arise due to differences in terminology, priorities, or documentation standards. Additionally, managing design iteration cycles, ensuring timely delivery of process design kits (PDKs), and resolving manufacturing discrepancies require strong problem-solving skills and adaptability. Successfully navigating these challenges involves proactive communication, meticulous attention to detail, and a deep understanding of both design and fabrication processes.

What is the difference between Contractual Silicon Foundry Interface Engineer vs Contractual Semiconductor Process Engineer?

AspectContractual Silicon Foundry Interface EngineerContractual Semiconductor Process Engineer
Primary FocusInterface management between foundry and clients, ensuring design compatibilityDevelopment and optimization of semiconductor manufacturing processes
Required SkillsKnowledge of foundry processes, design rules, and client communicationProcess engineering, equipment operation, and process optimization
Work EnvironmentFoundry facilities, client sites, design teamsCleanroom manufacturing facilities, R&D labs
Common CertificationsNone specific, often requires engineering degreesSimilar engineering degrees, process-specific certifications

The Contractual Silicon Foundry Interface Engineer primarily manages communication and coordination between the foundry and clients, focusing on design compatibility. In contrast, the Contractual Semiconductor Process Engineer concentrates on developing and refining manufacturing processes. Both roles require engineering backgrounds but differ in daily tasks and focus areas.

What is a Contractual Silicon Foundry Interface Engineer?

A Contractual Silicon Foundry Interface Engineer is a professional who acts as a liaison between semiconductor design teams and silicon foundries, typically working on a contract basis. Their main responsibilities include coordinating technical requirements, ensuring design compatibility with foundry processes, and troubleshooting manufacturing issues. They help to optimize the fabrication process and facilitate communication between the client and the foundry, often handling design rule checks, process documentation, and yield analysis. This role is essential for smooth chip production and successful product delivery in the semiconductor industry.

What are the key skills and qualifications needed to thrive as a Contractual Silicon Foundry Interface Engineer, and why are they important?

To thrive as a Contractual Silicon Foundry Interface Engineer, you need a solid background in semiconductor physics, process technology, and integrated circuit (IC) design, typically with a degree in electrical engineering or related fields. Familiarity with EDA tools (like Cadence, Synopsys), PDK management, and foundry process documentation is essential, as are knowledge of industry standards and IP integration. Strong communication, project management, and problem-solving skills help facilitate collaboration between design teams and foundry partners. These competencies are crucial for ensuring design manufacturability, timely project delivery, and successful coordination between all stakeholders in the silicon manufacturing process.
What cities are hiring for Contractual Silicon Foundry Interface Engineer jobs? Cities with the most Contractual Silicon Foundry Interface Engineer job openings:
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Contractual Silicon Foundry Interface Engineer jobs near you
Senior Foundry Engineer, Silicon Technology

Senior Foundry Engineer, Silicon Technology

Astera Labs

San Jose, CA

$122K - $168K/yr

Other

Posted 21 days ago

Job description

Job Description
We are seeking a Senior Foundry Engineer, Silicon Technology to support foundry engagement, silicon-to-model correlation, tapeout readiness, and yield improvement for advanced semiconductor products. This person will work closely with internal design, CAD layout, product engineering, test, reliability, operations teams and external foundry partners to identify risks, assess product impact, and drive timely resolution of process, PDK, model, DRC/DFM, and silicon-related issues.
 
Responsibilities Include
  • Silicon, process and yield correlation
    • Analyze process inline data, silicon test data, process drift and process correlation data 
    • Fine tune processes to optimize power, performance and yield
    • Help identify process related contributors to parametric drift, yield loss, leakage, reliability risk
    • Work with foundry and internal teams to investigate yield issues and process excursions
    • Perform layout analysis where needed to understand process sensitivity, failures
  • Tapeout and DFM support
    • Support product tapeouts, tapeout readiness reviews from a PDK, DRC/DFM, device model and reliability perspective
    • Run or coordinate DFM checks on products and summarize findings for design and layout teams
    • Coordinate between foundry and physical design teams to disposition waivers taking performance, leakage, manufacturability and reliability in mind
    • Document known PDK, model, DRC, DFM or process risks before tapeout
    • Maintain an internal PDK qualification database across foundries and process nodes to reduce tapeout risk from unnoticed PDK or model changes
  • Foundry and PDK support
    • Support technical interactions with foundry partners on PDK, device models, process assumptions, design rules, DRC/DFM decks and reliability collateral
    • Track PDK versions, model updates, DRC/DFM runset changes, and foundry signoff recommendations
    • Compare PDK changes across versions and summarize potential design, layout, model or signoff impact
  • Device model and circuit model evaluation
    • Validate model behavior across voltage bias, temperature, process corners, and relevant operating conditions
    • Compare silicon measurements against SPICE/model predictions and help identify model gaps
Basic Qualifications:
  • B.S or M.S in Electrical Engineering, Material science, Semiconductor engineering or a related technical field
  • 5+ years of experience in semiconductor device engineering, foundry interface, silicon technology, process integration, yield/process correlation
Required Experience:
  • Working knowledge of semiconductor process flows, device physics, manufacturability, reliability and yield drivers
  • Experience supporting tapeouts, PDK validation, models, DRC/DFM, silicon bring up
  • Experience analyzing silicon, wafer-level, process monitors, product test, characterization, or reliability data
  • Prior experience at a foundry, IDM, fabless semiconductor company or a PDK/enablement organization
  • Familiarity with SPICE models, process corners, device behavior, layout effects and silicon-to-model correlation
  • Ability to communicate technical issues clearly across design, CAD, layout, test, products engineering and external foundries
  • Familiarity with using TSMC as a foundry
Preferred Experience:
  • Experience with advanced FinFET, gate-all-around/nanosheet technologies and BiCMOS technologies
  • Experience with SRAM, analog/mixed signal, RF, Serdes, low power design constraints
  • Experience benchmarking foundry nodes using spice models on representative circuits
  • Experience using foundry models to simulate junction breakdowns, SOA, ESD, aging, reliability or device operating limits

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