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Chip Verification Lead Engineer Jobs (NOW HIRING)

krg technology inc

SoC verification Engineer

Boston, MA

$147K/yr

Working on full chip verification and OVM/UVM Methodology, System Verilog is a must with 2+years of recent work experience Worked on passing test cases, test benches, Building environment. Knowledge ...

TSMC

Physical Design Verification Lead (7264)

San Jose, CA · On-site

$155K - $160K/yr

Lead and execute end-to-end physical design verification for CPU blocks, culminating in successful production chip tapeouts. * Collaborate closely with the STA team to implement Engineering Change ...

AIT Global, Inc.

Design Verification Lead

San Jose, CA · On-site

$159K - $194K/yr

Design Verification Lead Location: San Jose/Portland USA Position Summary: We are looking for a ... Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.

Apple

Design Verification Lead

Cupertino, CA · On-site

$167K - $204K/yr

Are you a leader and want to apply your engineering background to make big things happen, and can ... We are looking for a remarkable Design Verification Lead to work with multi-functional teams and ...

Ekcel Systems

Design Verification Lead

San Jose, CA · On-site

$159K - $194K/yr

Design Verification Lead Experience: 8+ Years Location: San Jose/Portland USA Position Summary We ... Required Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer ...

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Chip Verification Lead Engineer information

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How much do chip verification lead engineer jobs pay per year?

As of Sep 10, 2026, the average yearly pay for chip verification lead engineer in the United States is $123,784.00, according to ZipRecruiter salary data. Most workers in this role earn between $102,500.00 and $135,000.00 per year, depending on experience, location, and employer.

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Infographic showing various Chip Verification Lead Engineer job openings in the United States as of August 2026, with employment types broken down into 87% Full Time, 10% Part Time, and 3% Contract. Highlights an 91% Physical, 3% Hybrid, and 6% Remote job distribution, with an average salary of $123,784 per year, or $59.5 per hour.

Principal Physical Verification Engineer

San Jose, CA

Celero Communications, Inc.
See more jobs at Celero Communications, Inc.external

$150K - $250K/yr

Full-time

Posted 23 days ago

Job description

Celero Communications, Inc. is an exciting and fast-growing semiconductor startup developing high-performance coherent digital signal processors (DSPs) for optical interconnects used in large-scale AI infrastructure. Celero's goal is to enable higher-bandwidth, lower-power optical connectivity between AI clusters and data centers.

We are seeking a Full-Chip Physical Verification Engineer to join our Physical Design team and help deliver complex digital blocks and full-chip implementations in advanced process technologies. This role will own all aspects of Physical Verification execution on advanced TSMC nodes, ensuring design quality, manufacturability, and tapeout readiness. The ideal candidate has successfully completed multiple tapeouts and brings deep expertise in physical verification methodologies, including driving improvements in quality, execution efficiency, and predictable delivery across multiple programs. You will work closely with the Analog Design and Physical Design teams to identify and resolve verification challenges while ensuring designs meet aggressive performance, manufacturability, and schedule objectives.

Locations: San Jose, CA (preferred) or Irvine, CA (HQ)

Key Responsibilities
Team & Project Leadership
Lead full chip Physical Verification effort
Own execution plans, schedules for full-chip
Drive accountability for quality, milestones, and tapeout readiness.
Conduct full chip and blocks PV checks

Physical Verification Ownership
Ownership of full chip verification
Work with internal analog team to ensure clean IP delivery
Responsible for running and analyzing DRC/ERC/LUP/PERC results
Experience with using either ICV or Calibre verification tools
Understanding advance TSMC DRC rules

Cross-Functional Collaboration
Partner with analog, block, chip top owners to ensure clean floorplan
Provide early guidance on corner case requirements
Influence floorplan constraints, hierarchy, and implementation strategy
Participate in tapeout readiness reviews

Required Qualifications
Bachelor's or Master's degree in Electrical Engineering or related field.
7+ years of experience with full-chip verifications
Proven hands-on experience with:
Physical Verification tool (ICV/Calibre)
Able to assemble a flow to support block/chip level PV
Strong expertise in:
Floorplanning to avoid DRC/LVS issues
Provide guidance to analog IP team to allow for clean integration

Preferred Qualifications
Experience in advanced technology nodes (7nm, 5nm, 3nm)
Automation skills using Tcl, Python, or shell scripting

Annual Base Salary Range: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location)

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