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Chip Scale Integration Jobs (NOW HIRING)

nEye.ai

Senior MEMS Design Engineer

Santa Clara, CA · On-site

The company's SuperSwitch is an ultra-low power consumption, high radix, compact chip-scale design ... Experience with advanced packaging technologies and their integration into the foundry process.

nEye.ai

Senior Silicon Photonics Designer

Santa Clara, CA · On-site

$175K - $250K/yr

The company's OCS is an ultra-low power consumption, high radix, compact chip-scale design ... Designing photonic components and photonic integrated circuits to advance our optical switch ...

nEye.ai

Senior Silicon Photonics Designer

Santa Clara, CA · On-site

$175K - $250K/yr

The company's OCS is an ultra-low power consumption, high radix, compact chip-scale design ... Designing photonic components and photonic integrated circuits to advance our optical switch ...

nEye.ai

Senior Silicon Photonics Designer

Santa Clara, CA · On-site

$119K - $128K/yr

The company's OCS is an ultra-low power consumption, high radix, compact chip-scale design ... Designing photonic components and photonic integrated circuits to advance our optical switch ...

Apple

Package Integration Engineer

Bodega Bay, CA

$181K - $318K/yr

In-depth knowledge in Wafer Level Chip Scale Packaging (RDL/Wafer Bumping & BEOL Assembly processes for Fan-In & Fan-Out designs). Expert level knowledge of common reliability failure modes. Able to ...

Etched

Chip Simulation Software Engineer

San Jose, CA · On-site

$200K - $250K/yr

Integrate multiple simulated chips to validate multi-chip software scale-out and scale-up approaches. * Work closely with Sohu software teams in debugging early software deliverables. Benefits

Etched

Chip Simulation Software Engineer

San Jose, CA · On-site

$200K - $250K/yr

Integrate multiple simulated chips to validate multi-chip software scale-out and scale-up approaches. * Work closely with Sohu software teams in debugging early software deliverables. Benefits

OMNIVISION

Product Validation Engineer

Santa Clara, CA · On-site

... chip scale testing. * Drive production yield rate reach to target yield level from new product tape ... Digital circuit design and hardware/software integration for system-level applications, with ...

OMNIVISION

Product Validation Engineer

Santa Clara, CA

$120K - $125K/yr

... chip scale testing. * Drive production yield rate reach to target yield level from new product tape ... Digital circuit design and hardware/software integration for system-level applications, with ...

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Chip Scale Integration information

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How much do chip scale integration jobs pay per hour?

As of Jun 7, 2026, the average hourly pay for chip scale integration in the United States is $29.84, according to ZipRecruiter salary data. Most workers in this role earn between $21.88 and $36.54 per hour, depending on experience, location, and employer.

What is the difference between Chip Scale Integration vs Microelectronics Engineer?

AspectChip Scale IntegrationMicroelectronics Engineer
Required CredentialsBachelor's or higher in Electrical Engineering or related fieldBachelor's or higher in Electrical Engineering, Microelectronics, or related field
Work EnvironmentDesign labs, manufacturing facilities, R&D centersDesign labs, fabrication facilities, R&D centers
Industry UsageSemiconductor, consumer electronics, telecommunicationsSemiconductor, integrated circuit design, electronics manufacturing

Chip Scale Integration involves designing and manufacturing highly integrated semiconductor devices, focusing on miniaturization and performance. Microelectronics Engineers work on designing, testing, and developing microelectronic circuits and systems. While both roles require similar educational backgrounds and work environments, Chip Scale Integration emphasizes the integration of multiple functions into a single chip, whereas Microelectronics Engineers focus on circuit design and development. Understanding these differences helps clarify career paths and job expectations in the electronics industry.

What is chip scale integration?

Chip scale integration refers to the technology and process of assembling and packaging integrated circuits (ICs) in a way that the package size is nearly the same as the chip itself. This approach minimizes the overall size of electronic devices, enhances performance, and can reduce manufacturing costs. Chip scale integration is commonly used in applications where space, weight, and power efficiency are critical, such as smartphones, wearables, and IoT devices.

What job makes $10,000 a month without a degree?

In the field of Chip Scale Integration, high-paying roles such as senior design engineers or technical managers can earn around $10,000 or more per month, often requiring specialized skills, experience, and industry certifications. These positions typically involve designing and testing integrated circuits and may require advanced knowledge of semiconductor fabrication and CAD tools, but they do not always require a traditional college degree if the candidate has substantial hands-on experience and expertise.

What are some common challenges faced by professionals in Chip Scale Integration, and how can they be addressed?

Professionals working in Chip Scale Integration often encounter challenges such as managing thermal issues, ensuring high-yield assembly, and maintaining signal integrity at increasingly smaller scales. Staying updated with the latest packaging technologies and collaborating closely with design, manufacturing, and testing teams can help address these challenges. Additionally, developing expertise in advanced simulation tools and actively participating in cross-functional meetings supports problem-solving and innovation in this rapidly evolving field.

What are the key skills and qualifications needed to thrive in Chip Scale Integration, and why are they important?

To excel in Chip Scale Integration, you need a solid background in electrical engineering, semiconductor physics, and microfabrication processes, typically with at least a bachelor’s or master’s degree in a related field. Proficiency in CAD software, semiconductor simulation tools, and familiarity with cleanroom protocols and industry standards such as IPC or JEDEC are highly valuable. Strong problem-solving skills, attention to detail, and effective cross-functional communication help professionals stand out in this role. These skills ensure the development of reliable, high-performance chip-scale devices and support innovation in advanced electronics manufacturing.
Infographic showing various Chip Scale Integration job openings in the United States as of May 2026, with employment types broken down into 92% Full Time, 5% Part Time, and 3% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $62,077 per year, or $29.8 per hour.
Chip Lead, Senior Director

Chip Lead, Senior Director

Astera Labs

San Jose, CA

Other

Posted 28 days ago

Job description

Astera Labs is seeking an Senior Director OR Associate Vice President, Product Technical Lead (Chip Lead) to drive the end-to-end success of our next-generation UALink switching products in San Jose. This is an executive technical leadership role where you will connect architecture, design, validation, firmware, systems, and operations to ensure clarity, alignment, and predictable execution across the full product lifecycle. 

As the technical integrator for the product line, you will lead through influence and cross-functional authority, working on cutting-edge UALink, UCIe, and PCIe Gen6/Gen7 technologies that power the largest AI clusters in the world. You'll be the central technical voice ensuring our switching products scale with Astera's hyper-growth while delivering world-class silicon to customers enabling rack-scale AI and hyperscale data centers. 

Location - San Jose, CA OR Israel 

Key Responsibilities 

  • Product Technical Ownership 
  • Own the full technical lifecycle of the product line-architecture assumptions, design integration, validation strategy, readiness, and customer enablement 
  • Drive chip development execution from RTL to GDSII, ensuring architecture, implementation, and tapeout milestones are met 
  • Lead development of large-scale chips (300-400mm) utilizing 2.5D/3D advanced packaging technologies and chiplet-based architectures 
  • Reduce ambiguity by translating product requirements into clear priorities, tradeoffs, and execution paths 
  • Own the Chip Tapeout and Chip signoff with full responsibility on Chip Quality.  
  • Cross-Functional Technical Leadership 
  • Anticipate challenges early, drive alignment across all engineering functions, ensuring risks, dependencies, and decisions are surfaced and resolved at the earliest 
  • Partner with design verification teams to define coverage goals, regression strategies, and sign-off criteria 
  • Collaborate with DFT teams on test architecture, scan insertion, BIST, and manufacturing test strategies 
  • Work closely with physical design teams on timing closure, power optimization, and backend execution 
  • Process Excellence & Organizational Development 
  • Establish and reinforce scalable processes, documentation, and handoffs that support company growth 
  • Provide structured, data-driven decision-making and maintain a crisp operational cadence across the product line 
  • Transform conflicts to foster a culture of ownership over ego, mentoring and elevating teams while strengthening technical judgment, accountability, and cross-functional collaboration 
  • Model steady, calm leadership, particularly in high-stakes or ambiguous situations 
  • Shape engineering culture and talent strategy to support Astera's rapid growth trajectory 

Basic Qualifications 

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field 
  • 15+ years of experience across architecture, silicon design, validation, systems, or related domains 
  • Proven track record of developing large-scale chips (300mm+) through successful tapeout 
  • Hands-on experience with 2.5D and 3D advanced packaging technologies and chiplet-based architectures 
  • Strong understanding of RTL design, design verification, DFT, and physical design flows 
  • Experience with high-speed serial interfaces such as PCIe, Ethernet, or switching architectures 
  • Demonstrated executive leadership of cross-functional technical programs with end-to-end product cycle ownership 
  • Strong communication and executive presence with the ability to influence at all levels of the organization 

Preferred Qualifications 

  • Master's degree in Electrical Engineering or Computer Engineering 
  • Experience with UALink, UCIe, PCIe Gen5/Gen6/Gen7, or Ethernet switching architectures 
  • Experience with advanced process nodes (7nm, 5nm, or below) 
  • Background in power management, clocking architectures, or high-speed analog integration 
  • Experience operating in fast-growing startups or hyper-scale environments 

Key Leadership Competencies 

  • Systems Thinking: See the big picture while managing details 
  • Emotional Intelligence: Calm under pressure, empathetic, and influential 
  • Adaptability: Thrive in ambiguity and fast-changing environments 
  • Execution Discipline: Deliver predictable results without sacrificing innovation 

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