Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). Research and develop software solutions to allow greater ...
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). Research and develop software solutions to allow greater ...
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). Research and develop software solutions to allow greater ...
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). Research and develop software solutions to allow greater ...
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). * Research and develop software solutions to allow greater ...
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). * Research and develop software solutions to allow greater ...
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). Research and develop software solutions to allow greater ...
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). Research and develop software solutions to allow greater ...
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). * Research and develop software solutions to allow greater ...
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). * Research and develop software solutions to allow greater ...
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). * Research and develop software solutions to allow greater ...
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). * Research and develop software solutions to allow greater ...
To accelerate our pathway to human ready brain-computer interfaces, you will have the opportunity to partner with our electrical, microfabrication, chip designers, neuro and mechanical engineers. Job ...
To accelerate our pathway to human ready brain-computer interfaces, you will have the opportunity to partner with our electrical, microfabrication, chip designers, neuro and mechanical engineers. Job ...
ASIC Physical Design Engineer
New York, NY · On-site
$148K - $153K/yr
We're a small team where everyone works across the chip design process, and we expect our PD engineers to lead with physical design expertise but think like chip designers. You should be comfortable ...
ASIC Physical Design Engineer
New York, NY · On-site
$148K - $153K/yr
We're a small team where everyone works across the chip design process, and we expect our PD engineers to lead with physical design expertise but think like chip designers. You should be comfortable ...
Research Scientist
San Jose, CA · On-site
$350K/yr
In this role, you'll conduct research that directly impacts chip designers, working at the intersection of cutting‑edge AI and real‑world semiconductor workflows. You'll train and deploy large ...
Research Scientist
San Jose, CA · On-site
$350K/yr
In this role, you'll conduct research that directly impacts chip designers, working at the intersection of cutting‑edge AI and real‑world semiconductor workflows. You'll train and deploy large ...
Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs * Perform ESD verification - validate protection strategies, current paths, and CDM/HBM compliance * Drive tapeout ...
Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs * Perform ESD verification - validate protection strategies, current paths, and CDM/HBM compliance * Drive tapeout ...
Chip Architect
San Francisco, CA · On-site
Today, chip development requires large teams, fragmented tools, and multi-year development cycles ... Requirements * 8+ years architecting and shipping complex chips or subsystems, with designs taken ...
Chip Architect
San Francisco, CA · On-site
Today, chip development requires large teams, fragmented tools, and multi-year development cycles ... Requirements * 8+ years architecting and shipping complex chips or subsystems, with designs taken ...
Research Scientist
San Jose, CA · On-site
$350K/yr
In this role, you'll conduct research that directly impacts chip designers, working at the intersection of cutting-edge AI and real-world semiconductor workflows. You'll train and deploy large ...
Research Scientist
San Jose, CA · On-site
$350K/yr
In this role, you'll conduct research that directly impacts chip designers, working at the intersection of cutting-edge AI and real-world semiconductor workflows. You'll train and deploy large ...
#Software Engineer - WLAN Santa Clara, California, United States of America Software Engineering Fle
Santa Clara, CA · On-site
You collaborate as a peer with chip designers, RF engineers, and hardware board engineers -- not just as a consumer of their work. * Mentorship and code quality: You actively raise the bar for junior ...
#Software Engineer - WLAN Santa Clara, California, United States of America Software Engineering Fle
Santa Clara, CA · On-site
You collaborate as a peer with chip designers, RF engineers, and hardware board engineers -- not just as a consumer of their work. * Mentorship and code quality: You actively raise the bar for junior ...
Digital IC Design Engineer Intern
South San Francisco, CA · On-site
$35/hr
You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As a Digital IC Design Engineer ...
Digital IC Design Engineer Intern
South San Francisco, CA · On-site
$35/hr
You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As a Digital IC Design Engineer ...
Chip Design Engineer
San Francisco, CA · On-site
... chip design ... Your designs will go into production at the world's leading technology companies. What You Will Do
Chip Design Engineer
San Francisco, CA · On-site
... chip design ... Your designs will go into production at the world's leading technology companies. What You Will Do
Analog IC Layout Engineer
South San Francisco, CA · On-site
$83K - $139K/yr
You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As an Analog IC Layout Engineer ...
Analog IC Layout Engineer
South San Francisco, CA · On-site
$83K - $139K/yr
You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As an Analog IC Layout Engineer ...
Sr Principal Engineer -SIPI
San Jose, CA · On-site
$154K - $286K/yr
Provide extracted and measured channel models for chip designers in the R&D team. Help with package and PCB SI/PI design guidelines and customer support on SI/PI related inquiries. Review customer ...
Sr Principal Engineer -SIPI
San Jose, CA · On-site
$154K - $286K/yr
Provide extracted and measured channel models for chip designers in the R&D team. Help with package and PCB SI/PI design guidelines and customer support on SI/PI related inquiries. Review customer ...
You collaborate as a peer with chip designers, RF engineers, and hardware board engineers -- not just as a consumer of their work. * Mentorship and code quality: You actively raise the bar for junior ...
You collaborate as a peer with chip designers, RF engineers, and hardware board engineers -- not just as a consumer of their work. * Mentorship and code quality: You actively raise the bar for junior ...
Sr Principal Engineer -SIPI
San Jose, CA · On-site
$154K - $286K/yr
... chip designers in the R&D team. • Help with package and PCB SI/PI design guidelines and customer support on SI/PI related inquiries. • Review customer package and board designs and simulation ...
Sr Principal Engineer -SIPI
San Jose, CA · On-site
$154K - $286K/yr
... chip designers in the R&D team. • Help with package and PCB SI/PI design guidelines and customer support on SI/PI related inquiries. • Review customer package and board designs and simulation ...
... chip designers. You drive net new logos and account expansion from prospecting through signed order form. You are equally comfortable explaining a physics model to a chief engineer and walking an ...
... chip designers. You drive net new logos and account expansion from prospecting through signed order form. You are equally comfortable explaining a physics model to a chief engineer and walking an ...
Chip Designers information
See salary details
$16.79 is the 25th percentile. Wages below this are outliers.
$10.10 - $18.36
31% of jobs
$18.36 - $26.62
16% of jobs
The median wage is $29.10 / hr.
$26.62 - $34.88
11% of jobs
$34.88 - $43.14
15% of jobs
$48.30 is the 75th percentile. Wages above this are outliers.
$43.14 - $51.40
4% of jobs
$51.40 - $59.66
6% of jobs
$59.66 - $67.92
5% of jobs
$67.92 - $76.18
3% of jobs
$76.18 - $84.44
2% of jobs
$84.44 - $92.70
3% of jobs
$92.70 - $100.96
3% of jobs
$10
$41
$100
How much do chip designers jobs pay per hour?
As of Sep 9, 2026, the average hourly pay for chip designers in the United States is $41.30, according to ZipRecruiter salary data. Most workers in this role earn between $17.55 and $58.41 per hour, depending on experience, location, and employer.
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For Chip Designers jobs, the most frequently searched job titles are:
Senior C++ Software Engineer - Chip Design Tools
Westford, MA
Nvidia •
Computer and Electronic Product Manufacturing • 10K+ employees10,000+ employees
Full-time
Re-posted 4 days ago
Nvidia rating
9.6
Based on 18 frontline employees who took The Breakroom Quiz
6th of 247 rated software companies
Job description
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing.
NVIDIA is a "learning machine" that constantly evolves by adapting to new challenges that are hard to tackle, that only we can pursue, and that matter to the world. This is our life's work, to amplify human creativity and intelligence. Make the choice to join us today.
Our team is responsible for development and support of infrastructure tools used by design engineers for build and verification of architectural, rtl, and gate level designs. As a software engineer, you will craft highly efficient software to automate and facilitate chip design and verification processes. What You'll be Doing: Work as a team to build reliable, scalable and high performance software that are easy to use by hundreds of engineers worldwide.
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). Research and develop software solutions to allow greater efficiency in architecture, hardware and software teams. Optimize the daily workflows of the world's top chip modelers and designers.
What We Need to See: BS (or equivalent experience) and 5+ years of software development experience., MS (or PHD) preferred. Experienced with C++ or Golang, Unix/Linux. Solid understanding of algorithms, computer architecture and computer science theory Experienced with VLSI frontend design and verification Flexibility/adaptability for working in a global and dynamic environment with different frameworks and requirements Ways to stand out from the crowd: Good architecture and RTL design knowledge Strong expertise in modern C++, compiler, build systems, and database
Experienced with static and dynamic code analysis tools Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 152,000 USD - 241,500 USD for Level 3, and 184,000 USD - 287,500 USD for Level 4. You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until July 11, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US