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Chip Design Jobs in Oregon (NOW HIRING)

Intel

Collateral Design and DFM Engineer

Hillsboro, OR

$140K - $168K/yr

Hands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs, Backside power delivery * Understanding of Physical Design flows for ...

Apple

Physical Design Engineer

Beaverton, OR

$141K - $145K/yr

Generate block/chip level static timing constraints. Build full chip floor-plan including pin ... Run Physical Design verification flow at chip/block level and provide guidelines to fix LVS/DRC ...

Apple

Physical Design Engineer

Beaverton, OR · On-site

$141K - $145K/yr

Generate block/chip level static timing constraints. Build full chip floor-plan including pin ... Run Physical Design verification flow at chip/block level and provide guidelines to fix LVS/DRC ...

Nvidia

OR · Hybrid

In the role of a Senior LPU ASIC Engineer, you will play a crucial role in our innovative LPU chip design. * Full-Flow Ownership: Responsible for Synthesis, floorplanning, place & route, timing ...

Apple

Custom Circuits Design Engineer

Beaverton, OR · On-site

We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...

K2 Space

OR

$190K - $280K/yr

Support chip bring-up and debug through close collaboration with post-silicon and test teams ... Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical ...

Apple

Custom Circuits Design Engineer

Beaverton, OR

$147K - $272K/yr

You will perform the following - - Develop custom circuits to improve chip power efficiency. - Work with power team, PD and architects to define specifications and requirements - Perform design ...

Apple

Custom Circuits Design Engineer

Beaverton, OR

$147K - $272K/yr

You will perform the following - - Develop custom circuits to improve chip power efficiency. - Work with power team, PD and architects to define specifications and requirements - Perform design ...

Siemens

Calibre Product Engineer

Wilsonville, OR · On-site

$109K - $197K/yr

As a Product Engineer, you will interface with leading chip design and manufacturing companies deploying existing technologies and defining new product requirements to meet future needs. You will ...

Intel

Physical Design Engineer for Core IP

Hillsboro, OR

$148K - $152K/yr

Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks. * Scripting in an interpreted language, minimum TCL in addition ...

Nvidia

Senior CPU Design Engineer

Hillsboro, OR · Hybrid

Support hardware engineering activities including chip floor plan, power/clock distribution, chip ... Highly proficient in logic design, Verilog and/or SystemVerilog, with a deep understanding of ...

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Chip Design information

See Oregon salary details

$44.4K

$121K

$213K

How much do chip design jobs pay per year?

As of Jun 26, 2026, the average yearly pay for chip design in Oregon is $121,050.00, according to ZipRecruiter salary data. Most workers in this role earn between $88,300.00 and $152,200.00 per year, depending on experience, location, and employer.

Is chip design in demand?

Chip design is in high demand due to the growth of electronics, consumer devices, and the semiconductor industry. Skilled chip designers with knowledge of hardware description languages and electronic design automation tools are sought after across technology sectors, with job opportunities expected to grow as technology advances.

What are the key skills and qualifications needed to thrive in the Chip Design position, and why are they important?

To excel in Chip Design, a strong background in electrical engineering, digital and analog circuit design, and semiconductor physics is typically required, often supported by a relevant engineering degree. Familiarity with electronic design automation (EDA) tools like Cadence, Synopsys, and Mentor Graphics, as well as proficiency in hardware description languages (HDLs) such as Verilog or VHDL, are standard prerequisites. Outstanding problem-solving skills, attention to detail, and the ability to collaborate closely with cross-functional teams set candidates apart. These competencies are essential for designing efficient, reliable integrated circuits and meeting the evolving needs of the semiconductor industry.

What are the typical career progression opportunities in a Chip Design role?

Chip Design offers a clear pathway for career growth, starting from entry-level positions such as Design Engineer or Verification Engineer and progressing to roles like Lead Designer, Project Manager, or Technical Architect. As you gain experience and demonstrate expertise, opportunities often open up in specialized areas such as physical design, timing analysis, or system architecture. Many professionals also advance to leadership or managerial positions, overseeing teams or entire design projects. Additionally, working in such a fast-evolving field keeps you engaged with the latest technologies and can provide options to transition into adjacent areas like product management or application engineering.

What is a Chip Design job?

A Chip Design job involves creating and developing semiconductor circuits used in electronic devices. Engineers in this field work on designing, verifying, and testing integrated circuits (ICs) to ensure performance, power efficiency, and reliability. They use specialized software tools for designing hardware and optimizing functionality. Chip designers collaborate with cross-functional teams to bring new processors, memory chips, or custom ASICs from concept to production. This role is crucial in industries like computing, telecommunications, and consumer electronics.

What engineers make $500,000?

Senior chip design engineers with extensive experience, advanced skills in hardware description languages, and leadership roles can earn $500,000 or more annually, especially in high-cost-of-living areas or at major technology companies. Achieving this level typically requires a strong track record, specialized expertise, and often stock options or bonuses as part of compensation packages.

How much do chip designers make?

Chip designers, also known as integrated circuit designers, typically earn between $80,000 and $150,000 annually, depending on experience, education, and location. Senior roles or those with specialized skills in hardware description languages and CAD tools can earn higher salaries, often exceeding $200,000.

How much do microchip designers make?

Microchip designers, also known as integrated circuit designers, typically earn between $80,000 and $150,000 annually, depending on experience, education, and location. Senior designers with specialized skills in hardware description languages and CAD tools can earn higher salaries, especially in technology hubs.
What are the most commonly searched types of Chip Design jobs in Oregon? The most popular types of Chip Design jobs in Oregon are:
What are popular job titles related to Chip Design jobs in Oregon? For Chip Design jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Chip Design jobs in Oregon look for? The top searched job categories for Chip Design jobs in Oregon are:
Chip Design jobs near you
Collateral Design and DFM Engineer

Collateral Design and DFM Engineer

Intel

Hillsboro, OR

$140K - $168K/yr

Full-time

Medical, Retirement, PTO

Posted 22 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 144 frontline employees who took The Breakroom Quiz

10th of 139 rated electronics manufacturers

Job description

Job Details:Job Description: 

About MDCEManufacturing Development and Customer Engineering (MDCE) is Intel's newest organization within Intel Foundry Technology Manufacturing (FTM). We bridge the critical gap between Technology Development (TD) and High-Volume Manufacturing (HVM), advancing technology nodes from initial product qualification to high-yield production across multiple products while enhancing technologies for our foundry customers. MDCE is also chartered to develop new technologies on mature node infrastructure to bring new solutions to new customers at reliable yield and performance and low cost, and this is where you are going to play a role.

Position OverviewAs a Collateral - Design and DFM Lead Engineer you will be at the heart of HVM and ramp of leading-edge advance logic technologies chartered with inventing and enhancing DFM methodologies for improving performance, yield and ramp across a diverse product portfolio.

Key Responsibilities

Lead cross functional teams across process integration/ device/ yield/ design/OPC/RET/DR and DTP/CAD teams to define and enhance Design for Manufacturability rules for enhanced yield /performance and faster ramp on advanced logic technologies

Enhance and feed silicon learning / sighting of yield issues for design teams to update layout /DTCO methodologies, flows to capture yield issues early in the design process

Work and refine yield tools/flows inside foundry and help in inline yield detection and optimization

Define/Refine DFM methodologies by understanding silicon process flows and predicting and developing rules for avoiding layout and design marginalities by working with cross functional teams

Ideally the candidate should demonstrate:

Excellent communication and collaboration skills with ability to interface effectively with design teams, process engineers, and external customers from diverse industry segments

    Qualifications:

    Minimum Qualifications

    • Master or Ph.D. degree in Electrical Engineering, Physics, or related field with 10+ years of experience in DTCO and/or DFM within semiconductor foundry or advanced technology development environment
    • Strong understanding of DTCO skills including understanding of SRAM, Standard cells, Process Integration, Yield, and Device.
    • Experience in leading cross functional group in defining derivative architectures including Design rules, transistors and interconnects
    • Experience in scribe line layout design and process monitoring structure development
    • Proven track record in foundry environment developing and implementing DFM solutions for varied customer requirements across multiple market segments

    Preferred Qualifications

    • Coding/Scripting knowledge beneficial
    • Ability to switch between multiple projects and ability to prioritize
    • Required exposure to foundry ecosystem with understanding of customer design flows and manufacturing constraints across various application domains
    • Hands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs, Backside power delivery
    • Understanding of Physical Design flows for Yield Analysis, DRC, and verification flows
    • Proficiency in design rule development, validation, and waiver management processes
    Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, Santa ClaraAdditional Locations:US, Arizona, Phoenix, US, Oregon, HillsboroBusiness group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

    We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

    Annual Salary Range for jobs which could be performed in the US: $190,650.00-269,150.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

    Work Model for this Role

    This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

    *

    ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

    What Intel employees say

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    Benefits

    Hours and flexibility

    Workplace

    Get the full story on Breakroom

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    About Intel

    Sourced by ZipRecruiter

    Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

    Industry

    Manufacturing

    Company size

    10,000+ Employees

    Headquarters location

    Santa Clara, CA, US

    Year founded

    1968

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