Our goal is to reimagine chip design using AI, cut down ASIC design time and cost, and enable a new era of ultra-efficient, domain-specific chips powering the future of computation. Born out of ...
Our goal is to reimagine chip design using AI, cut down ASIC design time and cost, and enable a new era of ultra-efficient, domain-specific chips powering the future of computation. Born out of ...
Senior Applied AI and AI Infrastructure Engineer - Chip Design and DFX
Santa Clara, CA · On-site
$127K - $173K/yr
Design-for-X Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions in AI for Chip Design and AI for Predictions in various use cases in manufacturing testing ...
Senior Applied AI and AI Infrastructure Engineer - Chip Design and DFX
Santa Clara, CA · On-site
$127K - $173K/yr
Design-for-X Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions in AI for Chip Design and AI for Predictions in various use cases in manufacturing testing ...
Product Engineer - AI-Driven Analog Chip Design - Santa Clara*
Santa Clara, CA · On-site
$151K - $182K/yr
Product Engineer - AI-Driven Analog Chip Design We are looking for experienced Product Engineers to join our growing team in Santa Clara, California and help define the next generation of AI-driven ...
Product Engineer - AI-Driven Analog Chip Design - Santa Clara*
Santa Clara, CA · On-site
$151K - $182K/yr
Product Engineer - AI-Driven Analog Chip Design We are looking for experienced Product Engineers to join our growing team in Santa Clara, California and help define the next generation of AI-driven ...
CPU Design Verification Engineer
Santa Clara, CA · On-site
$159K - $195K/yr
In this highly visible role, you will be at the center of a chip design effort collaborating with all disciplines, with a critical impact on getting functional products to millions of customers ...
CPU Design Verification Engineer
Santa Clara, CA · On-site
$159K - $195K/yr
In this highly visible role, you will be at the center of a chip design effort collaborating with all disciplines, with a critical impact on getting functional products to millions of customers ...
CPU Physical Design and Integration Engineer
Santa Clara, CA · On-site
$159K - $164K/yr
... • Full chip floorplan, area optimizations, block partitioning and pin placements • Own chip ... chip design cycle to drive signoff closure for tapeout • Work with the SOC team to meet IP ...
CPU Physical Design and Integration Engineer
Santa Clara, CA · On-site
$159K - $164K/yr
... • Full chip floorplan, area optimizations, block partitioning and pin placements • Own chip ... chip design cycle to drive signoff closure for tapeout • Work with the SOC team to meet IP ...
CPU Physical Design and Integration Engineer
Santa Clara, CA · On-site
$159K - $164K/yr
... chip level place and route (PnR), final CPU layout database construction, and verification (PDV) • Work with the Implementation/CAD teams during the entire chip design cycle to drive signoff ...
CPU Physical Design and Integration Engineer
Santa Clara, CA · On-site
$159K - $164K/yr
... chip level place and route (PnR), final CPU layout database construction, and verification (PDV) • Work with the Implementation/CAD teams during the entire chip design cycle to drive signoff ...
Physical Design Timing Engineer
$160K - $165K/yr
Work with chip-design and software teams driving DensityAI's AI accelerator program from first silicon through scale-out. What you'll do * Own Full chip and Block timing methodologies and execution ...
Physical Design Timing Engineer
$160K - $165K/yr
Work with chip-design and software teams driving DensityAI's AI accelerator program from first silicon through scale-out. What you'll do * Own Full chip and Block timing methodologies and execution ...
SoC Physical Design Engineer, Electrical Analysis
San Diego, CA · On-site
$144K - $148K/yr
Description - As a senior member of our SoC physical design team, you will be performing various electrical analyses at the block or chip level, including but not limited to: Gridcheck, ESD, Static ...
SoC Physical Design Engineer, Electrical Analysis
San Diego, CA · On-site
$144K - $148K/yr
Description - As a senior member of our SoC physical design team, you will be performing various electrical analyses at the block or chip level, including but not limited to: Gridcheck, ESD, Static ...
CPU Design Verification Engineer
Santa Clara, CA · On-site
$159K - $195K/yr
In this highly visible role, you will be at the center of a chip design effort collaborating with all disciplines, with a critical impact on getting functional products to millions of customers ...
CPU Design Verification Engineer
Santa Clara, CA · On-site
$159K - $195K/yr
In this highly visible role, you will be at the center of a chip design effort collaborating with all disciplines, with a critical impact on getting functional products to millions of customers ...
Play a crucial role in the proof-of-concept chip tapeout process, seeing your research transition ... Circuit Design Acumen: Possess a solid foundation in circuit design principles and hands-on ...
Play a crucial role in the proof-of-concept chip tapeout process, seeing your research transition ... Circuit Design Acumen: Possess a solid foundation in circuit design principles and hands-on ...
Play a crucial role in the proof-of-concept chip tapeout process, seeing your research transition ... Circuit Design Acumen: Possess a solid foundation in circuit design principles and hands-on ...
Play a crucial role in the proof-of-concept chip tapeout process, seeing your research transition ... Circuit Design Acumen: Possess a solid foundation in circuit design principles and hands-on ...
CPU Physical Design and Integration Engineer
Santa Clara, CA · On-site
$159K - $164K/yr
... • Full chip floorplan, area optimizations, block partitioning and pin placements • Own chip ... chip design cycle to drive signoff closure for tapeout • Work with the SOC team to meet IP ...
CPU Physical Design and Integration Engineer
Santa Clara, CA · On-site
$159K - $164K/yr
... • Full chip floorplan, area optimizations, block partitioning and pin placements • Own chip ... chip design cycle to drive signoff closure for tapeout • Work with the SOC team to meet IP ...
Senior SOC Design Engineer
Santa Clara, CA · On-site
$136 - $218.50/hr
Spot inefficiencies in the front‑end chip implementation process and propose actionable improvements * Ensure high-quality RTL delivery to the physical design team with thorough design quality ...
New
Senior SOC Design Engineer
Santa Clara, CA · On-site
$136 - $218.50/hr
Spot inefficiencies in the front‑end chip implementation process and propose actionable improvements * Ensure high-quality RTL delivery to the physical design team with thorough design quality ...
New
Architect is a frontier AI research and product lab for chip design, aiming to revolutionize chip design using AI. The Founding Member of Technical Staff will be responsible for post-training AI ...
Architect is a frontier AI research and product lab for chip design, aiming to revolutionize chip design using AI. The Founding Member of Technical Staff will be responsible for post-training AI ...
Analog Layout Engineer (Must- High speed Layout & Chip design) _Sanjose, CA(Onsite)_Only Xoriant W2
San Jose, CA · On-site
$110/hr
Need someone with strong experience in new chip design * In addition to being an individual contributor who can complete assigned tasks(who can bring new ideas, take initiative, and contribute to ...
Analog Layout Engineer (Must- High speed Layout & Chip design) _Sanjose, CA(Onsite)_Only Xoriant W2
San Jose, CA · On-site
$110/hr
Need someone with strong experience in new chip design * In addition to being an individual contributor who can complete assigned tasks(who can bring new ideas, take initiative, and contribute to ...
Front-End CAD Engineer
Cupertino, CA · On-site
$2.0K/mo
Ability to automate and optimize CAD workflows for chip design verification. * Ability to interface with EDA vendors as well as internal users, identify the internal needs and priorities and bring in ...
Front-End CAD Engineer
Cupertino, CA · On-site
$2.0K/mo
Ability to automate and optimize CAD workflows for chip design verification. * Ability to interface with EDA vendors as well as internal users, identify the internal needs and priorities and bring in ...
Front-End CAD Engineer
Cupertino, CA · On-site
$2.0K/mo
Ability to automate and optimize CAD workflows for chip design verification. * Ability to interface with EDA vendors as well as internal users, identify the internal needs and priorities and bring in ...
Front-End CAD Engineer
Cupertino, CA · On-site
$2.0K/mo
Ability to automate and optimize CAD workflows for chip design verification. * Ability to interface with EDA vendors as well as internal users, identify the internal needs and priorities and bring in ...
SoC Physical Design Engineer, PnR
San Jose, CA · On-site
$159K - $164K/yr
... chip design flow, physical synthesis, floor-planning, place and route (PnR), power grid, timing (STA), physical design verification (DRC/LVS), EMIR (Redhawk/Totem/Voltus). Responsibilities would ...
SoC Physical Design Engineer, PnR
San Jose, CA · On-site
$159K - $164K/yr
... chip design flow, physical synthesis, floor-planning, place and route (PnR), power grid, timing (STA), physical design verification (DRC/LVS), EMIR (Redhawk/Totem/Voltus). Responsibilities would ...
SoC Physical Design Engineer, Top Level
San Jose, CA · On-site
$159K - $164K/yr
Description • Work with the FE team to understand chip architecture and drive physical aspects early in the design cycle. • Work with the physical design team to drive methodologies and "best ...
SoC Physical Design Engineer, Top Level
San Jose, CA · On-site
$159K - $164K/yr
Description • Work with the FE team to understand chip architecture and drive physical aspects early in the design cycle. • Work with the physical design team to drive methodologies and "best ...
Ability to automate and optimize CAD workflows for chip design verification. * Ability to interface with EDA vendors as well as internal users, identify the internal needs and priorities and bring in ...
Ability to automate and optimize CAD workflows for chip design verification. * Ability to interface with EDA vendors as well as internal users, identify the internal needs and priorities and bring in ...
Chip Design information
See California salary details
$41.5K - $55.8K
4% of jobs
$55.8K - $70.1K
8% of jobs
$80.6K is the 25th percentile. Wages below this are outliers.
$70.1K - $84.4K
17% of jobs
The median wage is $97.7K / yr.
$84.4K - $98.7K
22% of jobs
$98.7K - $113K
15% of jobs
$113K - $127.3K
6% of jobs
$131.9K is the 75th percentile. Wages above this are outliers.
$127.3K - $141.6K
7% of jobs
$141.6K - $155.9K
7% of jobs
$155.9K - $170.2K
8% of jobs
$170.2K - $184.6K
2% of jobs
$184.6K - $198.9K
2% of jobs
$41.5K
$113K
$198.9K
How much do chip design jobs pay per year?
How to get a job in chip design?
What are the key skills and qualifications needed to thrive in chip design?
To excel in Chip Design, a strong background in electrical engineering, digital and analog circuit design, and semiconductor physics is typically required, often supported by a relevant engineering degree. Familiarity with electronic design automation (EDA) tools like Cadence, Synopsys, and Mentor Graphics, as well as proficiency in hardware description languages (HDLs) such as Verilog or VHDL, are standard prerequisites. Outstanding problem-solving skills, attention to detail, and the ability to collaborate closely with cross-functional teams set candidates apart. These competencies are essential for designing efficient, reliable integrated circuits and meeting the evolving needs of the semiconductor industry.
What are the typical career progression opportunities in chip design?
Chip Design offers a clear pathway for career growth, starting from entry-level positions such as Design Engineer or Verification Engineer and progressing to roles like Lead Designer, Project Manager, or Technical Architect. As you gain experience and demonstrate expertise, opportunities often open up in specialized areas such as physical design, timing analysis, or system architecture. Many professionals also advance to leadership or managerial positions, overseeing teams or entire design projects. Additionally, working in such a fast-evolving field keeps you engaged with the latest technologies and can provide options to transition into adjacent areas like product management or application engineering.
Is chip design a good career?
What is a chip design?
A Chip Design job involves creating and developing semiconductor circuits used in electronic devices. Engineers in this field work on designing, verifying, and testing integrated circuits (ICs) to ensure performance, power efficiency, and reliability. They use specialized software tools for designing hardware and optimizing functionality. Chip designers collaborate with cross-functional teams to bring new processors, memory chips, or custom ASICs from concept to production. This role is crucial in industries like computing, telecommunications, and consumer electronics.
How much do chip designers make?

Full-time
Re-posted 11 days ago
Job description
Architect is a frontier AI research and product lab for chip design. We build AI models and systems that can explore, design, optimize, and verify new hardware. Our goal is to reimagine chip design using AI, cut down ASIC design time and cost, and enable a new era of ultra-efficient, domain-specific chips powering the future of computation.
Born out of Stanford, our team blends researchers and engineers from Anthropic, Google DeepMind, NVIDIA, Meta SuperIntelligence Labs, Apple, and Intel. Backed by leading VCs and angels, including the Chief Scientist at Google, Stanford professors, and founders of chip companies, Architect currently operates in stealth, pushing the limits of AI4EDA and building the intelligence layer for the hardware revolution.
What You'll Do
As a Founding Member of the Technical Staff (ML infra) at Architect, you'll be responsible for the critical algorithms and infrastructure that our researchers depend on to train models. Your work will directly enable breakthroughs in AI capabilities in chip designs.
- Build, maintain, and improve the algorithms and engineering systems used to post-train models for chip designs, focusing obsessively on improving training speed and reliability
- Profile reinforcement learning and training pipelines to detect bottlenecks and implement optimizations for high-performance training setups .
- Collaborate closely with ML researchers to implement stable and fast versions of new finetuning recipes (like in RLHF/SFT) on different model architectures.
What We'd Like to See
Qualifications & Skills:
- Degree: PhD in Computer Science, EECS, Mathematics, or a closely related field. Preferably, specialization in Machine Learning, Systems, or Artificial Intelligence. Or BS/MS with a strong research engineering background from frontier labs.
- ML Infrastructure: Proven track record of building end-to-end ML pipelines, including data curation, preparation, and large-scale LLM finetuning (RLHF, SFT).
- Debugging & Optimization: Adept at diagnosing why training runs slow down, building instrumentation to monitor system health, and fixing complex issues in distributed environments.
- Execution: Results-oriented with a bias towards flexibility and impact. You pick up slack and enjoy pair programming.
Bonus:
- Experience with implementing LLM finetuning algorithms (such as RLHF) and modifying systems based on model architectures.
- Worked on the post-training or infra team at frontier labs like OpenAI, Anthropic, DeepMind, Mistral, MSL, Cohere, etc.
- Foundation in Electrical/Computer Engineering and chip-design or verification processes (not required, but a plus).
- Publications in top ML (NeurIPS, ICLR, ICML) or Systems (OSDI, SOSP) venues.
- Founding Engineer or early hire at an AI deeptech startup.
What We Offer
- Competitive salary and meaningful equity stake
- Fast-paced startup with autonomy and visible impact
- Cutting-edge AI-driven chip design challenges