We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team ... A strong background in computer architecture , cache coherency or high speed interconnects is ...
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team ... A strong background in computer architecture , cache coherency or high speed interconnects is ...
Platform Engineer -- Infra / Reliability Specialist
San Francisco, CA · On-site
$67.25 - $89.25/hr
The Platform Engineer -- Infra / Reliability Specialist will be responsible for designing and ... cache design, and local-first systems that require challenging fault tolerance and non-blocking bi ...
Platform Engineer -- Infra / Reliability Specialist
San Francisco, CA · On-site
$67.25 - $89.25/hr
The Platform Engineer -- Infra / Reliability Specialist will be responsible for designing and ... cache design, and local-first systems that require challenging fault tolerance and non-blocking bi ...
We are looking for an experienced engineer who can drive CPU multi-level cache subsystem ... design to target power, performance, area and timing goals • Verification - support the ...
We are looking for an experienced engineer who can drive CPU multi-level cache subsystem ... design to target power, performance, area and timing goals • Verification - support the ...
Architect the memory hierarchy : including multi-level cache controllers, scratchpad memory ... Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a closely related ...
Architect the memory hierarchy : including multi-level cache controllers, scratchpad memory ... Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a closely related ...
Strong understanding of computer architecture, memory systems, cache coherence, and high-speed on ... Fluency in programming/scripting languages (e.g., Python, C++) for architectural modeling, design ...
Strong understanding of computer architecture, memory systems, cache coherence, and high-speed on ... Fluency in programming/scripting languages (e.g., Python, C++) for architectural modeling, design ...
We are now looking for a Senior Logic Design Engineer. As a member of our CPU Logic Design Team ... A strong background in computer architecture, cache coherency or high speed interconnects is ...
We are now looking for a Senior Logic Design Engineer. As a member of our CPU Logic Design Team ... A strong background in computer architecture, cache coherency or high speed interconnects is ...
We are now looking for a Senior Logic Design Engineer. As a member of our CPU Logic Design Team ... A strong background in computer architecture, cache coherency or high speed interconnects is ...
We are now looking for a Senior Logic Design Engineer. As a member of our CPU Logic Design Team ... A strong background in computer architecture, cache coherency or high speed interconnects is ...
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team ... A strong background in computer architecture , cache coherency or high speed interconnects is ...
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team ... A strong background in computer architecture , cache coherency or high speed interconnects is ...
Architect the memory hierarchy : including multi-level cache controllers, scratchpad memory ... Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a closely related ...
Architect the memory hierarchy : including multi-level cache controllers, scratchpad memory ... Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a closely related ...
SRAM Circuit Design Engineer
Austin, TX · On-site
You and your team will apply engineering fundamentals and start from scratch if needed, bringing ... Knowledge of Cache design/architecture, memory hierarchy is a huge plus. * Working knowledge of RTL ...
SRAM Circuit Design Engineer
Austin, TX · On-site
You and your team will apply engineering fundamentals and start from scratch if needed, bringing ... Knowledge of Cache design/architecture, memory hierarchy is a huge plus. * Working knowledge of RTL ...
... Engineer to help shape their cloud architecture and improve their AI capabilities. The role ... cache design, and local-first systems that require challenging fault tolerance and non-blocking bi ...
... Engineer to help shape their cloud architecture and improve their AI capabilities. The role ... cache design, and local-first systems that require challenging fault tolerance and non-blocking bi ...
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team ... A strong background in computer architecture , cache coherency or high speed interconnects is ...
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team ... A strong background in computer architecture , cache coherency or high speed interconnects is ...
You and your team will apply engineering fundamentals and start from scratch if needed, bringing ... Knowledge of Cache design/architecture, memory hierarchy is a huge plus. * Working knowledge of RTL ...
You and your team will apply engineering fundamentals and start from scratch if needed, bringing ... Knowledge of Cache design/architecture, memory hierarchy is a huge plus. * Working knowledge of RTL ...
Microarchitect & RTL Design Engineer Location: Santa Clara, CA About the Role: We are seeking a ... Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and ...
Microarchitect & RTL Design Engineer Location: Santa Clara, CA About the Role: We are seeking a ... Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and ...
Microarchitect & RTL Design Engineer Location: Santa Clara, CA About the Role: We are seeking a ... Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and ...
Microarchitect & RTL Design Engineer Location: Santa Clara, CA About the Role: We are seeking a ... Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and ...
CPU Cache Microarchitect/RTL Engineer
Beaverton, OR · On-site
$184K - $324K/yr
Description As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the ... design to target power, performance, area and timing goals • Verification - support the ...
CPU Cache Microarchitect/RTL Engineer
Beaverton, OR · On-site
$184K - $324K/yr
Description As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the ... design to target power, performance, area and timing goals • Verification - support the ...
Platform Engineer -- Infra / Reliability Specialist
San Francisco, CA · On-site
$67.25 - $89.25/hr
The Platform Engineer -- Infra / Reliability Specialist will be responsible for designing and ... cache design, and local-first systems that require challenging fault tolerance and non-blocking bi ...
Platform Engineer -- Infra / Reliability Specialist
San Francisco, CA · On-site
$67.25 - $89.25/hr
The Platform Engineer -- Infra / Reliability Specialist will be responsible for designing and ... cache design, and local-first systems that require challenging fault tolerance and non-blocking bi ...
CPU Cache Microarchitect/RTL Engineer
Beaverton, OR · On-site
$184K - $324K/yr
Description As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the ... design to target power, performance, area and timing goals • Verification - support the ...
CPU Cache Microarchitect/RTL Engineer
Beaverton, OR · On-site
$184K - $324K/yr
Description As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the ... design to target power, performance, area and timing goals • Verification - support the ...
You and your team will apply engineering fundamentals and start from scratch if needed, bringing ... Knowledge of Cache design/architecture, memory hierarchy is a huge plus. * Working knowledge of RTL ...
You and your team will apply engineering fundamentals and start from scratch if needed, bringing ... Knowledge of Cache design/architecture, memory hierarchy is a huge plus. * Working knowledge of RTL ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
Description As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the ... design to target power, performance, area and timing goals • Verification - support the ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
Description As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the ... design to target power, performance, area and timing goals • Verification - support the ...
Cache Design Engineer information
See salary details
$40.5K - $51.2K
2% of jobs
$51.2K - $62K
11% of jobs
$67.7K is the 25th percentile. Wages below this are outliers.
$62K - $72.7K
23% of jobs
The median wage is $79.6K / yr.
$72.7K - $83.4K
22% of jobs
$83.4K - $94.1K
17% of jobs
$94.4K is the 75th percentile. Wages above this are outliers.
$94.1K - $104.9K
9% of jobs
$104.9K - $115.6K
6% of jobs
$115.6K - $126.3K
3% of jobs
$126.3K - $137K
3% of jobs
$137K - $147.8K
2% of jobs
$147.8K - $158.5K
1% of jobs
$40.5K
$88.2K
$158.5K
How much do cache design engineer jobs pay per year?
What are popular job titles related to Cache Design Engineer jobs?
For Cache Design Engineer jobs, the most frequently searched job titles are:

Senior Logic Design Engineer, Cache Coherent Interconnects
Santa Clara, CA • Hybrid
Full-time
Re-posted 29 days ago
Nvidia rating
9.6
Based on 18 frontline employees who took The Breakroom Quiz
Job description
We are now looking for a Senior Logic Design Engineer!
As a member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip and off-chip interconnect network, MP coherency and last-level and system caches, focusing on such tasks as micro-architectural definition, RTL coding, logic debug, synthesis and timing closure, supporting verification and implementation. This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence! We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
What you'll be doing:
As a member of our core CPU team, you'll own and be responsible for crafting and timely delivery of a specific unit on the chip.
Day to day tasks include: writing readable high performance and low power RTL, Synthesis and Timing closure, and design documentation.
Collaborate with our verification team to verify the correctness of your unit.
Work with implementation to achieve your timing, area, performance and power goals.
Assist with timing closure of super units.
What we need to see:
Master's Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.
5+ years of experience in processor or other related high performance semiconductor designs.
Verilog expertise required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
Strong communication and interpersonal skills are required along with the work in a dynamic, global team. Your successful track record of mentoring junior engineers and interns a huge plus.
A strong background in computer architecture, cache coherency or high speed interconnects is helpful
NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most brilliant and hardworking people in the world working for us. Are you creative and autonomous and love the challenge of crafting the fastest and most power efficient chips in their class? If so, we want to hear from you.
#LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US