Description Design and develop hardware for cache subsystem in high performance system on a chip (SoC). Develop cache micro-architecture based on architecture guidelines and model analysis. Explore ...
Description Design and develop hardware for cache subsystem in high performance system on a chip (SoC). Develop cache micro-architecture based on architecture guidelines and model analysis. Explore ...
Description Design and develop hardware for cache subsystem in high performance system on a chip (SoC). Develop cache micro-architecture based on architecture guidelines and model analysis. Explore ...
Description Design and develop hardware for cache subsystem in high performance system on a chip (SoC). Develop cache micro-architecture based on architecture guidelines and model analysis. Explore ...
Description Design and develop hardware for cache subsystem in high performance system on a chip (SoC). Develop cache micro-architecture based on architecture guidelines and model analysis. Explore ...
Description Design and develop hardware for cache subsystem in high performance system on a chip (SoC). Develop cache micro-architecture based on architecture guidelines and model analysis. Explore ...
ASIC Design Engineer - Cache Controller
$150K - $277K/yr
Description Design and develop hardware for cache subsystem in high performance system on a chip (SoC). Develop cache micro-architecture based on architecture guidelines and model analysis. Explore ...
ASIC Design Engineer - Cache Controller
$150K - $277K/yr
Description Design and develop hardware for cache subsystem in high performance system on a chip (SoC). Develop cache micro-architecture based on architecture guidelines and model analysis. Explore ...
GPU RTL Design Engineer
Orlando, FL · On-site
Description As a GPU Design Engineer, you will participate in micro-architecture specification and ... areas of cache design, on-chip interconnect network, data compression or shader processor ...
GPU RTL Design Engineer
Orlando, FL · On-site
Description As a GPU Design Engineer, you will participate in micro-architecture specification and ... areas of cache design, on-chip interconnect network, data compression or shader processor ...
ASIC Design Engineer - Cache Controller
Santa Clara, CA · On-site
$129K - $194K/yr
Description Design and develop hardware for cache subsystem in high performance system on a chip (SoC). Develop cache micro-architecture based on architecture guidelines and model analysis. Explore ...
ASIC Design Engineer - Cache Controller
Santa Clara, CA · On-site
$129K - $194K/yr
Description Design and develop hardware for cache subsystem in high performance system on a chip (SoC). Develop cache micro-architecture based on architecture guidelines and model analysis. Explore ...
GPU RTL Design Engineer
Orlando, FL · On-site
Description As a GPU Design Engineer, you will participate in micro-architecture specification and ... Knowledge in one or more areas of cache design, on-chip interconnect network, data compression or ...
GPU RTL Design Engineer
Orlando, FL · On-site
Description As a GPU Design Engineer, you will participate in micro-architecture specification and ... Knowledge in one or more areas of cache design, on-chip interconnect network, data compression or ...
ASIC Design Engineer - Cache Controller
Santa Clara, CA · On-site
$184K - $324K/yr
Description Design and develop hardware for cache subsystem in high performance system on a chip (SoC). Develop cache micro-architecture based on architecture guidelines and model analysis. Explore ...
ASIC Design Engineer - Cache Controller
Santa Clara, CA · On-site
$184K - $324K/yr
Description Design and develop hardware for cache subsystem in high performance system on a chip (SoC). Develop cache micro-architecture based on architecture guidelines and model analysis. Explore ...
GPU RTL Design Engineer
Orlando, FL · On-site
Description As a GPU Design Engineer, you will participate in micro-architecture specification and ... areas of cache design, on-chip interconnect network, data compression or shader processor ...
GPU RTL Design Engineer
Orlando, FL · On-site
Description As a GPU Design Engineer, you will participate in micro-architecture specification and ... areas of cache design, on-chip interconnect network, data compression or shader processor ...
ASIC Design Engineer - Cache Controller
Santa Clara, CA · On-site
$184K - $324K/yr
Description Design and develop hardware for cache subsystem in high performance system on a chip (SoC). Develop cache micro-architecture based on architecture guidelines and model analysis. Explore ...
ASIC Design Engineer - Cache Controller
Santa Clara, CA · On-site
$184K - $324K/yr
Description Design and develop hardware for cache subsystem in high performance system on a chip (SoC). Develop cache micro-architecture based on architecture guidelines and model analysis. Explore ...
GPU RTL Design Engineer
Orlando, FL · On-site
Description As a GPU Design Engineer, you will participate in micro-architecture specification and ... Knowledge in one or more areas of cache design, on-chip interconnect network, data compression or ...
GPU RTL Design Engineer
Orlando, FL · On-site
Description As a GPU Design Engineer, you will participate in micro-architecture specification and ... Knowledge in one or more areas of cache design, on-chip interconnect network, data compression or ...
Role and Responsibilities As an Engineer or Senior or Staff GPU RTL Design Engineer, you will ... datapath, cache and memory systems. You bring curiosity, RTL design knowledge, and ...
Role and Responsibilities As an Engineer or Senior or Staff GPU RTL Design Engineer, you will ... datapath, cache and memory systems. You bring curiosity, RTL design knowledge, and ...
Role and Responsibilities As an Engineer or Senior or Staff GPU RTL Design Engineer, you will ... datapath, cache and memory systems. You bring curiosity, RTL design knowledge, and ...
Role and Responsibilities As an Engineer or Senior or Staff GPU RTL Design Engineer, you will ... datapath, cache and memory systems. You bring curiosity, RTL design knowledge, and ...
Role and Responsibilities As an Engineer or Senior or Staff GPU RTL Design Engineer, you will ... datapath, cache and memory systems. You bring curiosity, RTL design knowledge, and ...
Role and Responsibilities As an Engineer or Senior or Staff GPU RTL Design Engineer, you will ... datapath, cache and memory systems. You bring curiosity, RTL design knowledge, and ...
$164K - $269K/yr
... Engineer to drive the design and development of advanced memory circuits for future CPU and SoC ... Cache design, critical path simulations and design custom blocks. * Memory path-finding activities ...
$164K - $269K/yr
... Engineer to drive the design and development of advanced memory circuits for future CPU and SoC ... Cache design, critical path simulations and design custom blocks. * Memory path-finding activities ...
Memory Circuit Design Engineer
Austin, TX · On-site
$164K - $269K/yr
... Engineer to drive the design and development of advanced memory circuits for future CPU and SoC ... Cache design, critical path simulations and design custom blocks. * Memory path-finding activities ...
Memory Circuit Design Engineer
Austin, TX · On-site
$164K - $269K/yr
... Engineer to drive the design and development of advanced memory circuits for future CPU and SoC ... Cache design, critical path simulations and design custom blocks. * Memory path-finding activities ...
Cache design, critical path simulations and design custom blocks to meet stringent Power ... A Bachelor's degree in Electrical /Computer Engineering, or a STEM-related field with 4+ years of ...
Cache design, critical path simulations and design custom blocks to meet stringent Power ... A Bachelor's degree in Electrical /Computer Engineering, or a STEM-related field with 4+ years of ...
Memory Circuit Design Engineer
Austin, TX · On-site
... Engineer to drive the design and development of advanced memory circuits for future CPU and SoC ... Cache design, critical path simulations and design custom blocks. * Memory path-finding activities ...
Memory Circuit Design Engineer
Austin, TX · On-site
... Engineer to drive the design and development of advanced memory circuits for future CPU and SoC ... Cache design, critical path simulations and design custom blocks. * Memory path-finding activities ...
Cache design, critical path simulations and design custom blocks to meet stringent Power ... A Bachelor's degree in Electrical /Computer Engineering, or a STEM-related field with 4+ years of ...
Cache design, critical path simulations and design custom blocks to meet stringent Power ... A Bachelor's degree in Electrical /Computer Engineering, or a STEM-related field with 4+ years of ...
Cache design, critical path simulations and design custom blocks to meet stringent Power ... Note: A Bachelor's degree in Electrical /Computer Engineering, or a STEM-related field with 4+ ...
Cache design, critical path simulations and design custom blocks to meet stringent Power ... Note: A Bachelor's degree in Electrical /Computer Engineering, or a STEM-related field with 4+ ...
Cache Design Engineer information
See salary details
$40.5K - $51.2K
2% of jobs
$51.2K - $62K
11% of jobs
$67.7K is the 25th percentile. Wages below this are outliers.
$62K - $72.7K
23% of jobs
The median wage is $79.6K / yr.
$72.7K - $83.4K
22% of jobs
$83.4K - $94.1K
17% of jobs
$94.4K is the 75th percentile. Wages above this are outliers.
$94.1K - $104.9K
9% of jobs
$104.9K - $115.6K
6% of jobs
$115.6K - $126.3K
3% of jobs
$126.3K - $137K
3% of jobs
$137K - $147.8K
2% of jobs
$147.8K - $158.5K
1% of jobs
$40.5K
$88.2K
$158.5K
How much do cache design engineer jobs pay per year?
As of Sep 13, 2026, the average yearly pay for cache design engineer in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.
What are popular job titles related to Cache Design Engineer jobs?
For Cache Design Engineer jobs, the most frequently searched job titles are:
ASIC Design Engineer - Cache Controller
Santa Clara, CA • On-site
Apple
• Computer and Electronic Product Manufacturing • 10K+ employees10,000+ employees
Full-time
Re-posted 7 days ago
Apple rating
8.1
Based on 684 frontline employees who took The Breakroom Quiz
Job description
Apple is building the world's fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency, and high-bandwidth. In this role, you will work on crafting special purpose cache and controller which is part and parcel of the SOC memory hierarchy.
Description
Design and develop hardware for cache subsystem in high performance system on a chip (SoC).
Develop cache micro-architecture based on architecture guidelines and model analysis.
Explore architecture trade-offs in system performance, area, and power consumption.
Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem.
Work on front-end netlist and area/timing analysis of the cache subsystem.
Work with physical design team on the timing closure of the cache subsystem.
Minimum Qualifications
3+ years of full time ASIC design experience
memory system development
RTL/micro-architecture definition
PPA (performance/power/area) analysis
B.S. in a relevant field
Preferred Qualifications
Cache design background including good understanding of different memory organizations and tradeoffs
Experience with multi-processor cache coherence protocols
Knowledge of high-performance coherent memory systems or interconnect architectures
Knowledge of high-performance DRAM controller
M.S in a relevant field.
Description
Design and develop hardware for cache subsystem in high performance system on a chip (SoC).
Develop cache micro-architecture based on architecture guidelines and model analysis.
Explore architecture trade-offs in system performance, area, and power consumption.
Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem.
Work on front-end netlist and area/timing analysis of the cache subsystem.
Work with physical design team on the timing closure of the cache subsystem.
Minimum Qualifications
3+ years of full time ASIC design experience
memory system development
RTL/micro-architecture definition
PPA (performance/power/area) analysis
B.S. in a relevant field
Preferred Qualifications
Cache design background including good understanding of different memory organizations and tradeoffs
Experience with multi-processor cache coherence protocols
Knowledge of high-performance coherent memory systems or interconnect architectures
Knowledge of high-performance DRAM controller
M.S in a relevant field.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976