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Asic Jobs in Raleigh, NC (NOW HIRING)

Nvidia

Principal CPU Software Architect

Durham, NC · On-site

Your role will be cross disciplinary, collaborating with industry partners, customers, internal architects, software, ASIC design, verification, and platform teams. Our software architects excel at ...

Nvidia

Senior Security Architect - Hardware

Durham, NC · On-site

Experience with the ASIC design process and architecture of large SoCs or GPUs. * Programming and debugging fundamentals across languages such as: C/C++, Verilog, ARM assembly and Python/Perl ...

Nvidia

EDA Workflow Optimization Engineer

Durham, NC · Hybrid

$107K - $127K/yr

Experience with ASIC, VLSI, CAD/EDA or mixed signal design workflow environments. * Hands-on experience with EDA tools. * Experienced in UNIX Systems programming and automation using Python and/or ...

Avnet, Inc.

Field Application Engineer

Raleigh, NC

Experience with and understanding at systems level, FPGA and ASIC design tools. Experience with Vivado/Vitis, ISE or Quartus required (ModelSim is a plus) * Ability to identify a customer's key care ...

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Showing results 41-58

All JobsAsic JobsAsic Jobs in Raleigh, NC

Asic information

See Raleigh, NC salary details

$91.4K

$146K

$196.3K

How much do asic jobs pay per year?

As of Aug 6, 2026, the average yearly pay for asic in Raleigh, NC is $145,994.00, according to ZipRecruiter salary data. Most workers in this role earn between $127,800.00 and $175,000.00 per year, depending on experience, location, and employer.

What are some common challenges faced by ASIC engineers during the chip design and verification process?

ASIC engineers often encounter challenges such as balancing power, performance, and area constraints while meeting tight project deadlines. Ensuring design correctness through thorough verification and debugging complex issues can be demanding, especially when integrating multiple IP blocks. Collaboration with cross-functional teams—including hardware, software, and test engineers—is essential to resolve challenges efficiently. Staying updated with evolving EDA tools and methodologies also plays a key role in overcoming these hurdles.

What is the difference between Asic vs FPGA Engineer?

AspectAsicFPGA Engineer
Required CredentialsBachelor's or higher in Electrical Engineering, VLSI Design, or related fields; certifications like Certified FPGA Designer are commonSimilar educational background; often the same certifications apply, especially in digital design
Work EnvironmentDesigning and developing custom integrated circuits in a semiconductor lab or design houseDeveloping programmable logic solutions using FPGA boards in labs or on-site environments
Industry UsageUsed in high-volume, performance-critical applications like consumer electronics, automotive, and telecommunicationsCommon in prototyping, testing, and specialized applications requiring flexibility

In summary, Asic and FPGA engineers share similar educational backgrounds and certifications. Asic engineers focus on designing custom chips for high-volume applications, while FPGA engineers work on programmable logic devices for flexible, rapid prototyping and testing. Both roles are vital in the semiconductor and electronics industries, often overlapping in skills and tools used.

What is an ASIC engineer?

ASIC engineers are professionals who design, develop, and test Application-Specific Integrated Circuits (ASICs). These are specialized microchips created for a particular application or product, such as smartphones, networking equipment, or automotive systems. ASIC engineers work on the entire chip design process, including architecture, logic design, verification, and sometimes physical layout. Their expertise ensures that the chips are efficient, reliable, and tailored to meet specific performance requirements.

What are the key skills and qualifications needed to thrive as an ASIC engineer, and why are they important?

To thrive as an ASIC Engineer, you need a solid background in electrical or computer engineering, digital design, and experience with hardware description languages like Verilog or VHDL. Familiarity with EDA tools such as Cadence or Synopsys and relevant certifications (e.g., in ASIC design or verification) are highly valuable. Strong analytical thinking, attention to detail, and effective teamwork skills set top performers apart in this role. These competencies are crucial for developing reliable, high-performance chips that meet complex specifications and project goals.

Is ASIC a good career?

ASIC (Application-Specific Integrated Circuit) design and engineering is a specialized field within electronics and semiconductor industries. It offers opportunities for high technical skill development, competitive salaries, and involvement in cutting-edge technology, but it often requires strong knowledge of digital design, hardware description languages, and industry certifications. The career can be rewarding for those interested in hardware development and engineering innovation.
What are popular job titles related to Asic jobs in Raleigh, NC? For Asic jobs in Raleigh, NC, the most frequently searched job titles are:
What job categories do people searching Asic jobs in Raleigh, NC look for? The top searched job categories for Asic jobs in Raleigh, NC are:
Asic jobs near you
Infographic showing various Asic job openings in Raleigh, NC as of July 2026, with employment types broken down into 95% Full Time, 2% Part Time, and 3% Contract. Highlights an 85% Physical, 9% Hybrid, and 6% Remote job distribution, with an average salary of $145,994 per year, or $70.2 per hour.

Principal Engineer - Design For Test (DFT)

Marvell

Morrisville, NC

Full-time

Life, Retirement

Re-posted 13 days ago

Job description

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

As a Digital IC Design Principal Engineer with Marvell, you'll be a member of the Custom Silicon Engineering team. This team is a leader in large multi-die designs that drive high compute performance and acceleration in many markets, including custom AI, 5G and 6G. The role will be challenging and will require an experienced DFT engineer that can work with existing DFT solutions while also creating new solutions to address industry first issues.

What You Can Expect

The position will be responsible for implementing DFT/Test on complex IP and SOC for multiple custom/compute ASIC/SoC designs. The work will involve running Tessent tools for insertion of all DFT structures. The role will involve chiplet DFT solutions, will include Tessent SSN, and will require strong verification and debug skills.

  • The engineer will need to show proficiency in ICL/PDL, PTAP/STAP, 1687. It is a requirement that the engineer is knowledgeable in instrument-level access inside a chip.
  • The engineer will work with other leads to help with Design-for-Test architecture definition and implementation of additional DFT/DFX features
  • The engineer will also be involved in STA constraint definition, pattern generation & post-silicon bring-up and debug.
  • In this position, the responsibility will grow to include mentoring, guiding and driving a small team of DFT engineers.
  • The engineer will work with other leads to help enhance DFT methodologies and tools.

What We're Looking For

  • Bachelor's, Master's degree or PhD in Computer Science, Electrical Engineering or related fields with minimum of 10 years of work experience.
  • Direct DFT experience with at least 8 years in the custom chip (ASIC) design business
  • Hands-on working experience in various stages of DFT-Execution: SCAN/MBIST/Validation/STA/IP-DFX/Post-Silicon Bring-up/Debug
  • Thorough knowledge on various DFT/Test architecture solutions for 2.5D/3D IC design.
  • Strong fundamentals in digital circuit design and logic design
  • Understanding of DFT flows and methodologies and experience with Siemens/Synopsys Tool set (Tessent, Spyglass/Tmax, Genus, Modus, NCSim/DC), with Tessent the EDA tool flow in use.
  • Proven track record of problem solving and innovation to meet challenging design requirements.
  • Excellent team player and can work with different function leaders, across different geographies to define and execute the DFT project to completion.
  • Excellent communications skills both verbal and written.
  • Scripting skills using Python, PERL, Tcl and C-Shell is plus.

Expected Base Pay Range (USD)

160,400 - 237,320, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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