SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power ...
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power ...
SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ...
SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ...
... SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power ...
... SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power ...
FPGA/ASIC Design Engineer (Silicon Engineering)
Redmond, WA · On-site
$140K - $175K/yr
Design ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC ... ASIC Design Engineer/Level I: $125,000.00 - $145,000.00/per year ASIC Design Engineer/Level II: ...
FPGA/ASIC Design Engineer (Silicon Engineering)
Redmond, WA · On-site
$140K - $175K/yr
Design ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC ... ASIC Design Engineer/Level I: $125,000.00 - $145,000.00/per year ASIC Design Engineer/Level II: ...
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine, CA · On-site
$160K - $220K/yr
... SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power ...
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine, CA · On-site
$160K - $220K/yr
... SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power ...
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Sunnyvale, CA · On-site
$170K - $230K/yr
... SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power ...
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Sunnyvale, CA · On-site
$170K - $230K/yr
... SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power ...
Sr. ASIC DFT Engineer (Silicon)
$155K - $185K/yr
... ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ...
Sr. ASIC DFT Engineer (Silicon)
$155K - $185K/yr
... ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ...
... ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ...
... ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ...
Sr. ASIC DFT Engineer (Silicon)
Irvine, CA · On-site
$145K - $175K/yr
... ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ...
Sr. ASIC DFT Engineer (Silicon)
Irvine, CA · On-site
$145K - $175K/yr
... ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ...
Sr. ASIC DFT Engineer (Silicon)
Irvine, CA · On-site
$145K - $175K/yr
SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ...
Sr. ASIC DFT Engineer (Silicon)
Irvine, CA · On-site
$145K - $175K/yr
SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ...
... ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ...
... ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ...
Sr. ASIC DFT Engineer (Silicon)
Sunnyvale, CA · On-site
$155K - $185K/yr
... ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ...
Sr. ASIC DFT Engineer (Silicon)
Sunnyvale, CA · On-site
$155K - $185K/yr
... ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ...
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San Jose, CA · On-site
$194K/yr
Senior ASIC ENGINEER Location : San Jose,CA - Onsite Duration : Permanent Direct Hire About the job ... Hands-on experience implementing ARM RAS features: error detection, reporting/poisoning, fault ...
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ASIC Engineer
San Jose, CA · On-site
$194K/yr
Senior ASIC ENGINEER Location : San Jose,CA - Onsite Duration : Permanent Direct Hire About the job ... Hands-on experience implementing ARM RAS features: error detection, reporting/poisoning, fault ...
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Redmond, WA · On-site
$140K - $175K/yr
Design ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC ... ASIC Design Engineer/Level I: $125,000.00 - $145,000.00/per year ASIC Design Engineer/Level II: ...
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Redmond, WA · On-site
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Design ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC ... ASIC Design Engineer/Level I: $125,000.00 - $145,000.00/per year ASIC Design Engineer/Level II: ...
Sr. ASIC DFT Engineer (Silicon)
Sunnyvale, CA · On-site
$155K - $185K/yr
SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ...
Sr. ASIC DFT Engineer (Silicon)
Sunnyvale, CA · On-site
$155K - $185K/yr
SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ...
ASIC Design for Test (DFT) Engineer (Remote)
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ASIC Design for Test (DFT) Engineer (Remote)
Williston, VT · On-site +1
$100K - $165K/yr
Responsibilities As an ASIC Design for Test Engineer , you will be part of a customer team ... Primary responsibilities include the architecture and implementation of Design for Test structures ...
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San Jose, CA · On-site
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Senior ASIC ENGINEER Location : San Jose,CA - Onsite Duration : Permanent Direct Hire About the job ... Hands-on experience implementing ARM RAS features: error detection, reporting/poisoning, fault ...
ASIC Engineer
San Jose, CA · On-site
$194K/yr
Senior ASIC ENGINEER Location : San Jose,CA - Onsite Duration : Permanent Direct Hire About the job ... Hands-on experience implementing ARM RAS features: error detection, reporting/poisoning, fault ...
Sr. ASIC DFT Engineer (Silicon)
$145K - $175K/yr
... ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ...
Sr. ASIC DFT Engineer (Silicon)
$145K - $175K/yr
... ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ...
Sr. ASIC DFT Engineer (Silicon)
Sunnyvale, CA · On-site
$155K - $185K/yr
... ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ...
Sr. ASIC DFT Engineer (Silicon)
Sunnyvale, CA · On-site
$155K - $185K/yr
... ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ...
... ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ...
... ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Implement and optimize DFT architectures, including scan insertion, compression/decompression logic ...
Asic Implementation Engineer information
See salary details
$26.92 - $31.82
4% of jobs
$31.82 - $36.71
13% of jobs
$39.02 is the 25th percentile. Wages below this are outliers.
$36.71 - $41.61
18% of jobs
$41.61 - $46.50
14% of jobs
The median wage is $47.39 / hr.
$46.50 - $51.40
11% of jobs
$51.40 - $56.29
8% of jobs
$59.41 is the 75th percentile. Wages above this are outliers.
$56.29 - $61.19
11% of jobs
$61.19 - $66.08
8% of jobs
$66.08 - $70.98
7% of jobs
$70.98 - $75.87
3% of jobs
$75.87 - $80.77
2% of jobs
$26
$51
$80
How much do asic implementation engineer jobs pay per hour?
What are the key skills and qualifications needed to thrive as an ASIC Implementation Engineer, and why are they important?
What are ASIC Implementation Engineers?
What are some common challenges faced by ASIC Implementation Engineers during the physical design phase?
What is the difference between Asic Implementation Engineer vs FPGA Design Engineer?
| Aspect | Asic Implementation Engineer | FPGA Design Engineer |
|---|---|---|
| Required Credentials | Bachelor's/Master's in Electrical Engineering or Computer Engineering, knowledge of ASIC design tools | Bachelor's/Master's in Electrical Engineering or Computer Engineering, FPGA design experience |
| Work Environment | Semiconductor companies, chip design firms, hardware development labs | Embedded systems companies, FPGA vendors, hardware startups |
| Industry Usage | Used in ASIC chip development for consumer electronics, automotive, and telecom | Used in prototyping, testing, and custom hardware solutions |
| Common Search/Comparison | Often compared due to overlapping hardware design skills and industry applications |
The Asic Implementation Engineer focuses on translating ASIC design into manufacturable chips, working with synthesis, placement, and routing. The FPGA Design Engineer specializes in designing and testing FPGA-based hardware solutions. While both roles require hardware description language skills and knowledge of digital design, they differ in their end products and development environments.

$160K - $220K/yr
Other
Medical, Dental, Vision, Life, Retirement, PTO
Posted 11 days ago
SpaceX rating
8.7
Based on 143 frontline employees who took The Breakroom Quiz
12th of 59 rated aerospace companies
Job description
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
- Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
- Develop/improve physical design methodologies and automation scripts for various implementation steps
- Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
- Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
- Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop
BASIC QUALIFICATIONS:
- Bachelor's degree in electrical engineering, computer engineering or computer science
- 5+ years of ASIC and/or physical design flow development experience in industry
PREFERRED SKILLS AND EXPERIENCE:
- Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
- Strong experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
- Knowledge of deep sub-micron FinFET and CMOS solid state physics
- Knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
- Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
- Familiar with CMOS analog circuit and physical design
- Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
- Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
- Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment
ADDITIONAL REQUIREMENTS:
- Ability to work extended hours and weekends as needed to meet critical project milestones
COMPENSATION AND BENEFITS:
Pay range:
Physical Design Engineer/Senior: $160,000.00 - $220,000.00/per year
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.
Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.
About SpaceX
Sourced by ZipRecruiter
Industry
Accounting services
Company size
1,001 - 5,000 Employees
Headquarters location
Hawthorne, CA, US
Year founded
2002