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Asic Design Engineering Intern Jobs (NOW HIRING)

Jr. ASIC Design Engineer

Batavia, NY · Hybrid

$70K - $93K/yr

We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and ... Bachelor's degree in an applicable Engineering discipline from an ABET accredited institution.

SR. ASIC DESIGN ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch ... Bachelor's degree in electrical engineering, computer engineering, or computer science. * 5+ years ...

Jr. ASIC Design Engineer

Batavia, IL · On-site

$70K - $93K/yr

We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and ... Bachelor's degree in an applicable Engineering discipline from an ABET accredited institution.

We are looking for a Sr. ASIC Design Engineer! NVIDIA is seeking best-in-class ASIC Design ... Proven hardware engineering background with a concentration in VLSI and Computer Architecture

SR. ASIC DESIGN ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch ... Bachelor's degree in electrical engineering, computer engineering, or computer science. * 5+ years ...

Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals ... ASIC design experience, delivering silicon from microarchitecture, specification, and RTL coding ...

Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals ... ASIC design experience, delivering silicon from microarchitecture, specification, and RTL coding ...

... Engineering, or related field. * 10+ years of industry experience in ASIC/SoC design with a focus ... on PCIe controller integration. * Proven experience in silicon bring-up and debug of high-speed ...

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Asic Design Engineering Intern information

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How much do asic design engineering intern jobs pay per hour?

As of Jun 15, 2026, the average hourly pay for asic design engineering intern in the United States is $19.38, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $21.63 per hour, depending on experience, location, and employer.

What is the difference between Asic Design Engineering Intern vs FPGA Design Intern?

AspectAsic Design Engineering InternFPGA Design Intern
Required SkillsHardware description languages (Verilog/VHDL), digital design, EDA toolsFPGA development, hardware description languages, simulation tools
Work EnvironmentSemiconductor companies, chip design teamsFPGA development labs, electronics firms
Industry UsageASIC chip manufacturing, integrated circuit designPrototyping, testing, and FPGA-based applications

While both roles involve digital hardware design and similar tools, an Asic Design Engineering Intern focuses on designing and developing custom integrated circuits, whereas an FPGA Design Intern works primarily with programmable logic devices for rapid prototyping and testing. The roles share skills but differ in application and end products.

What cities are hiring for Asic Design Engineering Intern jobs? Cities with the most Asic Design Engineering Intern job openings:
What states have the most Asic Design Engineering Intern jobs? States with the most job openings for Asic Design Engineering Intern jobs include:
Infographic showing various Asic Design Engineering Intern job openings in the United States as of June 2026, with employment types broken down into 97% Full Time, and 3% Contract. Highlights an 86% Physical, 4% Hybrid, and 10% Remote job distribution, with an average salary of $40,304 per year, or $19.4 per hour.
Principal ASIC Design Engineer (Starshield)

Principal ASIC Design Engineer (Starshield)

SpaceX

Irvine, CA

$200K - $285K/yr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Posted 12 days ago


SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 144 frontline employees who took The Breakroom Quiz

13th of 60 rated aerospace companies


Job description

PRINCIPAL ASIC DESIGN ENGINEER (STARSHIELD)

Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. As an ASIC Design Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. You will work in a highly collaborative and fast-paced environment, where we are exploring unsolved problems and applying the SpaceX mindset of iterating rapidly to go from design and demo to operational capability at lightning pace.

RESPONSIBILITIES:

  • Design digital ASICs and/or FPGAs for Starshield projects.
  • Evaluate architectural trade-offs based on features, performance requirements and system limitations. Derive specifications for the subsystems and circuits, and work with modem/DSP and RFIC engineers to partition functions between hardware and software domains.
  • Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
  • Work closely with verification team to ensure all aspects of the design are covered and verified.
  • Provide timing constraints for those IPs and support the physical implementation team (synthesis, timing closure, formality check).
  • Participate in silicon bring-up and validation. Assist in the development of automated test lab equipment for lab measurements.

BASIC QUALIFICATIONS:

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 8+ years of experience in RTL implementation and/or FPGA/ASIC development.

PREFERRED SKILLS AND EXPERIENCE:

  • Experience solving problems including clock domain crossings and power optimization.
  • Experience developing complex ASICs.
  • Experience with multicore CPU subsystem design.
  • Experience with standard bus protocols (e.g. AXI, AHB, etc.).
  • Experience with embedded processors.
  • Experience with high speed and low power design techniques.
  • Scripting skills (Python, TCL etc.).
  • Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado, Altera Quartus II).
  • Ability to work in a dynamic environment with changing needs and requirements.
  • Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis.
  • Enjoy being challenged and learning new skills.

ADDITIONAL REQUIREMENTS:

  • Ability to work long hours and weekends as necessary to support critical milestones.
  • Willingness to travel for off-site testing.
  • An active TS-SCI clearance may provide the opportunity for you to work on sensitive SpaceX missions; if so, you will be subject to pre-employment drug and random drug and alcohol testing.

COMPENSATION AND BENEFITS:    

Pay range:    
Principal ASIC Design Engineer: $200,000.00 - $285,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience. Those with an active clearance will receive a 10% differential, up to an additional $15,000 annually, once officially briefed into a classified program.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.


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