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Asic Design Engineering Intern Jobs in Texas (NOW HIRING)

Conductor

ASIC Design Engineer

Austin, TX · On-site

We're looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer. Ideal ...

Atom Computing

Senior ASIC Design Engineer

Austin, TX

$140K - $175K/yr

MS or PhD in Electrical Engineering, or related field. * 5+ years of post-degree experience as a hardware engineer. Qualifications * Have gone through a complete ASIC design cycle * Experience in ...

Atom Computing

Senior ASIC Design Engineer

Austin, TX · On-site

$140K - $175K/yr

MS or PhD in Electrical Engineering, or related field. * 5+ years of post-degree experience as a hardware engineer. Qualifications * Have gone through a complete ASIC design cycle * Experience in ...

Atom Computing

Senior ASIC Design Engineer

Austin, TX · On-site

$140K - $175K/yr

MS or PhD in Electrical Engineering, or related field. * 5+ years of post-degree experience as a hardware engineer. Qualifications * Have gone through a complete ASIC design cycle * Experience in ...

Cornelis Networks

PCIe ASIC Design Engineer

Austin, TX · On-site

... Engineering, or related field. * 10+ years of industry experience in ASIC/SoC design with a focus ... on PCIe controller integration. * Proven experience in silicon bring-up and debug of high-speed ...

Cornelis Networks

PCIe ASIC Design Engineer

Austin, TX · On-site +1

... Engineering, or related field. * 10+ years of industry experience in ASIC/SoC design with a focus ... on PCIe controller integration. * Proven experience in silicon bring-up and debug of high-speed ...

Positron AI

ASIC Design Engineer

Austin, TX · On-site

$225K - $350K/yr

Role Overview As a Senior ASIC Design Engineer, you will take a leadership role in defining, implementing, and delivering critical IP blocks and subsystems for Positron.ai's inference ASICs/SoCs. You ...

Positron AI

ASIC Design Engineer

Austin, TX · On-site

$225K - $350K/yr

As a Senior ASIC Design Engineer, you will take a leadership role in defining, implementing, and delivering critical IP blocks and subsystems for Positron.ai's inference ASICs/SoCs. You will own the ...

Nvidia

Senior ASIC Floorplan Design Engineer

Austin, TX · On-site

We are now looking for a Senior ASIC Floorplan Design Engineer. NVIDIA is seeking a talented ASIC ... Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent ...

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Asic Design Engineering Intern information

What is the difference between Asic Design Engineering Intern vs FPGA Design Intern?

AspectAsic Design Engineering InternFPGA Design Intern
Required SkillsHardware description languages (Verilog/VHDL), digital design, EDA toolsFPGA development, hardware description languages, simulation tools
Work EnvironmentSemiconductor companies, chip design teamsFPGA development labs, electronics firms
Industry UsageASIC chip manufacturing, integrated circuit designPrototyping, testing, and FPGA-based applications

While both roles involve digital hardware design and similar tools, an Asic Design Engineering Intern focuses on designing and developing custom integrated circuits, whereas an FPGA Design Intern works primarily with programmable logic devices for rapid prototyping and testing. The roles share skills but differ in application and end products.

What cities in Texas are hiring for Asic Design Engineering Intern jobs?

Cities in Texas with the most Asic Design Engineering Intern job openings:

Infographic showing various Asic Design Engineering Intern job openings in Texas as of August 2026, with employment types broken down into 86% Full Time, 10% Part Time, and 4% Contract. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution.

ASIC Design Engineer

Austin, TX • On-site

Conductor
See more jobs at Conductorexternal

Other

Re-posted 2 days ago

Job description

We’re looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer.

Ideal Background:
  • Hands-on experience with multiple advanced node tapeouts
  • Ownership of ASIC design portion of at least one block in multiple advanced node tapeouts
  • Understanding of PPA improvement and what levers exist for each level of the stack
  • Ability to think creatively about methodology for fast design iterations
Nice to Have:
  • Hands-on experience with ASIC design process for large die (ideally reticle max) chips
  • Hands-on experience with ASIC design process for AI chips
  • Hands-on experience with multi-die/multi-chiplet/MCM designs
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