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Ai Chip Design Rtl Jobs in Hoboken, NJ (NOW HIRING)

jobr.pro

Hardware Engineer, FPGA

Manhattan, NY · On-site

$100 - $130/hr

We co-design the full stack: AI-native EDA systems in production with the world's largest ... RTL Implementation: Adapt and implement complex ASIC RTL onto FPGA targets, including multi-clock ...

1014 AD Federal

Staff RF Design Engineer

Elizabeth, NJ · On-site

$131 - $190/hr

ADI combines analog, digital, AI, and software technologies into solutions that combat climate ... Design and evaluate complex multi-chip designs and architectures from DC to 40GHz+ * Identify ...

New

Nvidia

HPC Middleware Developer

Holmdel, NJ

Our team works closely with networking chip design teams in co-designing new hardware features and ... Today, we stand at the beginning of the next era, the AI computing era, ignited by a new computing ...

Normal Computing

AI Research Engineer

New York, NY · On-site

$200K - $400K/yr

You'll design and run experiments, build agents, curate datasets from complex technical documents ... Familiarity with semiconductor/chip domains or other complex technical specs. * Track record of ...

Normal Computing

Software Engineer, Backend

New York, NY · On-site

$200K - $400K/yr

We co-design the full stack: AI-native EDA systems in production with the world's largest ... real chip design environments, a web product for managing projects and reviewing results, and ...

Lantern

Senior Lead, AI Automation

New York, NY

$150K - $190K/yr

Ultimately, this role directly impacts Lantern's ability to deliver care to members, win blue-chip ... Design and build AI solutions that resolve the root cause, rather than bolting automation onto a ...

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All JobsAi Chip Design Rtl JobsAi Chip Design Rtl Jobs in Hoboken, NJ

Ai Chip Design Rtl information

See Hoboken, NJ salary details

$88.1K

$152.5K

$199.7K

How much do ai chip design rtl jobs pay per year?

As of Aug 23, 2026, the average yearly pay for ai chip design rtl in Hoboken, NJ is $152,480.00, according to ZipRecruiter salary data. Most workers in this role earn between $148,800.00 and $148,800.00 per year, depending on experience, location, and employer.

What is an AI Chip Design RTL engineer?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What skills and qualifications are needed to thrive as an AI Chip Design RTL engineer?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.

What are common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

What cities near Hoboken, NJ are hiring for Ai Chip Design Rtl jobs?

Cities near Hoboken, NJ with the most Ai Chip Design Rtl job openings:

Ai Chip Design Rtl jobs near you
Infographic showing various Ai Chip Design Rtl job openings in Hoboken, NJ as of August 2026, with employment types broken down into 88% Full Time, 8% Part Time, and 4% Contract. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution, with an average salary of $152,480 per year, or $73.3 per hour.

Hardware Engineer, FPGA

jobr.pro

Manhattan, NY • On-site

$100 - $130/hr

Other

Posted 17 days ago

Job description

About Normal Computing

Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. Conventional chips spend most of their energy forcing determinism onto physics; ours compute with it. Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt.

We co-design the full stack: AI-native EDA systems in production with the world's largest semiconductor companies, and the advanced ASICs they make possible. Backed by $85M+ from the world's leading deep-tech investors and built by scientists, engineers, and operators from the labs that built modern computing.

Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire people who want the hardest version of their craft, across every discipline, at every seniority.

The Role

Validating conventional silicon is a solved discipline. Validating silicon that computes with noise is not, and you will be the one who figures out how. As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early software development, and building the test infrastructure for post-silicon bring-up and characterization. Your scope spans the entire FPGA lifecycle: selecting hardware platforms, implementing complex RTL, debugging in the lab, and writing the software that drives it all, working daily with our silicon, EDA, and research teams.

What You'll Own

  • FPGA Platform Ownership: Lead the selection, procurement, and bring-up of FPGA prototyping platforms (e.g., HAPS, VCU118/VPK180-class boards, or custom hardware) for pre-silicon RTL validation and software development.

  • RTL Implementation: Adapt and implement complex ASIC RTL onto FPGA targets, including multi-clock-domain architectures, CDC bridges, and timing closure on dense designs.

  • IP Integration: Integrate in-house designs with third-party and vendor IP; serve as the expert on the AMD/Xilinx ecosystem (Vivado IP Integrator, transceivers, memory controllers).

  • High-Speed Interfaces: Design, implement, and validate high-speed I/O with a focus on PCIe: our accelerators ship as PCIe cards in standard servers.

  • Post-Silicon Validation: Build FPGA-based "tester" designs for silicon bring-up, device characterization, and automated test environments.

  • Hardware-Software Stack: Develop the software layer around the hardware: Python/C++ hardware abstraction, register-map generation, and automated build and regression flows.

  • Lab Debug: Root-cause complex timing and functional issues in real time using ILA/Vivado Analyzer, oscilloscopes, logic analyzers, and BER/eye-diagram characterization of high-speed links.

What Makes You a Great Fit

  • Proven industry experience taking FPGA designs from RTL through timing closure to validated hardware, ideally in an ASIC prototyping, emulation, or high-growth hardware environment.

  • Expert-level SystemVerilog and/or VHDL for synthesis, with deep proficiency in Xilinx Vivado (synthesis, place & route, timing closure, IP catalog).

  • Hands‑on experience implementing and debugging PCIe, plus AXI/AHB, SPI, UART, JTAG, and other common interfaces.

  • Strong Python for automation, test, and build tooling.

  • Strong board‑level bring‑up and lab debugging skills on real hardware.

  • Startup mindset: you work independently, pivot quickly, and run at ambiguous problems that span hardware, software, and physics.

Bonus Points

  • Verification frameworks like Cocotb, UVM, or OSVVM.

  • Experience deploying ML models to FPGAs (hls4ml, FINN, or custom NN‑to‑RTL flows), or building real‑time, sub‑microsecond signal processing pipelines.

  • Mixed‑signal ASIC exposure: digital front‑ends, ADC/DAC interfaces, or analog compute.

  • SERDES tuning and signal integrity fundamentals.

  • CI/CD for hardware (GitLab CI, Docker‑based build and test).

Equal Employment Opportunity Statement

Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.

Accessibility Accommodations

Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.

Privacy Notice

By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment‑related purposes in accordance with our Privacy Policy.

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