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Ai Based Chip Design Intern Jobs (NOW HIRING)

Eridu AI

ASIC Chip Design Lead

Saratoga, CA · On-site

$250K - $280K/yr

... based hardware startup pioneering infrastructure solutions that accelerate AI data centers to ... Position Overview We are seeking a hands-on ASIC Chip Design Lead to own chip design execution from ...

Tenstorrent University Jobs

$50/hr

This role is onsite, based out of Austin, TX or Santa Clara, CA. Who You Are * Currently pursuing a ... Industry-standard tools and techniques for modern chip development * How top-tier silicon teams ...

DoubleVerify

Creative Design Intern

New York, NY · On-site

Experience with Generative AI and/or AI Agent creation. * Illustration background a plus. * Motion ... The successful candidate's starting salary will be determined based on a number of non ...

Landor

Design Intern

Chicago, IL · Hybrid

We are seeking a Full-Time Design Intern for Summer 2026. Could this be you? We are Landor, part of ... Please note that interns must be based near our Chicago studio for a hybrid working schedule (at ...

Landor

Design Intern

Chicago, IL · On-site

We are seeking a Full-Time Design Intern for Summer 2026. Could this be you? We are Landor, part of ... Please note that interns must be based near our Chicago studio for a hybrid working schedule (at ...

SiFive

CPU Design Intern

Santa Clara, CA · On-site

$32.40 - $39/hr

... of chip design, including artificial intelligence, machine learning, automotive, data center ... We have a market-based pay structure which varies by location. Please note that the base pay range ...

Full Spectrum Marketing

Graphic Design Intern

Akron, OH · On-site

$14.25 - $19.25/hr

Availability: Up to 15 hours per week (with the opportunity for more based on client needs ... AI Integration: Use AI to work efficiently and make the most of tools/assets available to you.

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How much do ai based chip design intern jobs pay per hour?

As of May 30, 2026, the average hourly pay for ai based chip design intern in the United States is $19.38, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $21.63 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an AI Based Chip Design Intern, and why are they important?

To thrive as an AI Based Chip Design Intern, you need a solid understanding of digital circuit design, computer architecture, and a background in electrical engineering or computer science. Familiarity with hardware description languages (such as Verilog or VHDL), AI frameworks (like TensorFlow or PyTorch), and electronic design automation (EDA) tools is typically required. Strong analytical thinking, problem-solving abilities, and effective communication skills help interns collaborate and innovate within multidisciplinary teams. These skills and qualities are crucial for successfully contributing to the development of advanced, efficient AI hardware solutions.

What types of projects and daily tasks can an AI-Based Chip Design Intern expect to work on?

As an AI-Based Chip Design Intern, you can expect to work on projects that involve modeling, simulating, and optimizing integrated circuits using AI-driven methodologies. Typical daily tasks may include assisting in developing and testing machine learning algorithms for hardware design automation, analyzing data from chip simulations, and collaborating closely with senior engineers to improve chip performance or power efficiency. You’ll likely get hands-on experience with industry-standard tools such as Python, TensorFlow, and EDA software, while participating in team meetings to discuss design challenges and solutions.

What are AI Based Chip Design Interns?

AI Based Chip Design Interns are students or early-career professionals who assist in the development of semiconductor chips that utilize artificial intelligence technologies. They typically work under the guidance of engineers to help design, test, and optimize chips for AI applications such as machine learning, deep learning, or neural networks. Their responsibilities can include running simulations, analyzing data, and supporting the hardware-software integration process. This internship provides hands-on experience in chip design, exposure to current industry tools, and insights into the rapidly evolving AI hardware field.
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ASIC Chip Design Lead

Eridu AI

Saratoga, CA • On-site

$250K - $280K/yr

Full-time

Posted 26 days ago

Job description

About Eridu
Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today's AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.
The company's solutions and value proposition have been widely validated by leading hyperscalers.
Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world's leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems.
Visit our website eridu.ai to learn more.
Position Overview
We are seeking a hands-on ASIC Chip Design Lead to own chip design execution from micro-architecture through full-chip integration and timing signoff. This role sits between senior individual contributor and technical lead: you will personally drive RTL and micro-architecture while providing execution leadership across design, verification, and physical design teams.
This is a highly technical, roll-up-your-sleeves role for someone who has taken chips to tape-out, understands what breaks late in the cycle, and knows how to drive designs to closure in a fast-paced startup environment.
Responsibilities
Hands-on RTL Development
  • Write, review, and debug production-quality RTL in Verilog/SystemVerilog
  • Own RTL blocks end-to-end from specification through signoff
  • Make timing-, area-, and power-aware design decisions at the RTL and micro-architecture levels
  • Perform detailed code reviews and set a high technical bar for RTL quality
Micro-Architecture Specification
  • Draft detailed micro-architecture specifications derived from architecture documents and feature requirements
  • Translate high-level requirements into implementable pipelines, control logic, datapaths, interfaces, and corner-case handling
  • Clearly define performance, latency, and resource tradeoffs to unblock RTL and verification execution
Physical-Design-Aware Design & Timing Closure
  • Work closely with Physical Design to improve synthesis and place-and-route timing.
  • Iterate on RTL, hierarchy, micro-architecture, and floorplanning to address timing, congestion, and QoR issues
  • Analyze synthesis and P&R reports and proactively drive timing, area, and power improvements
Verification Collaboration & Debug
  • Partner with Design Verification to debug functional and performance issues
  • Review functional and code coverage and provide actionable feedback
  • Own bugs from discovery through fix, validation, and closure
Full-Chip Integration & Signoff
  • Own full-chip RTL integration and block roll-up
  • Run chip-level synthesis, define constraints, and close chip-level timing
  • Deliver timing-clean netlists to Physical Design that meet performance targets
Execution Discipline & Technical Leadership
  • Drive block- and chip-level design checklists as execution quality gates
  • Review checklist status with designers and proactively push closure of open items
  • Continuously refine design methodologies, checklists, and flows based on silicon learnings
  • Lead by technical authority and hands-on execution rather than coordination alone

Qualifications
  • Strong hands-on experience with RTL design and micro-architecture
  • Proven experience with full-chip integration and timing closure
  • Led at least one full-chip tape-out within the last 3 years, with direct responsibility for design signoff and PD handoff
  • Deep understanding of synthesis, static timing analysis, and physical-design collaboration
  • Experience refactoring and restructuring RTL to resolve timing, area, and congestion challenges
  • Comfortable working cross-functionally with architecture, verification, firmware, and physical design teams
  • Demonstrated ability to drive execution in ambiguous, fast-moving environments

Nice to Have
  • Silicon bring-up experience, including post-silicon debug and RTL-to-silicon correlation
  • Hands-on experience defining and refining SDC constraints and improving post-layout timing
  • Knowledge of high-performance networking architectures and Ethernet-based systems
  • Familiarity with Ultra Ethernet and/or UCIe chip-to-chip interconnect protocols
  • Experience with chiplet-based system design

Why Join Us?
At Eridu, you'll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.
The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.
Notice to Recruiting Agencies
Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.
The pay range for this role is:
250,000 - 280,000 USD per year (Saratoga, CA)

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