Mixed Signal Logic Design Engineer
$122K - $232K/yr
This position is not eligible for an intel immigration sponsorship. Preferred Qualifications ... DDR Design domain knowledge with good hold on DFI/DDR/LPDDR protocols * VSCode GitHub CoPilot or ...

$122K - $232K/yr
This position is not eligible for an intel immigration sponsorship. Preferred Qualifications ... DDR Design domain knowledge with good hold on DFI/DDR/LPDDR protocols * VSCode GitHub CoPilot or ...
$122K - $232K/yr
This position is not eligible for an intel immigration sponsorship. Preferred Qualifications ... DDR Design domain knowledge with good hold on DFI/DDR/LPDDR protocols * VSCode GitHub CoPilot or ...
Santa Clara, CA · On-site
$141K - $200K/yr
Intel is seeking a Design Verification Engineer for the Silicon Chassis team. In this role, you ... You will work closely with senior engineers to build and execute robust verification plans, develop ...
Santa Clara, CA · On-site
$141K - $200K/yr
Intel is seeking a Design Verification Engineer for the Silicon Chassis team. In this role, you ... You will work closely with senior engineers to build and execute robust verification plans, develop ...
$122K - $232K/yr
This position is not eligible for an intel immigration sponsorship. Preferred Qualifications ... DDR Design domain knowledge with good hold on DFI/DDR/LPDDR protocols * VSCode GitHub CoPilot or ...
$122K - $232K/yr
This position is not eligible for an intel immigration sponsorship. Preferred Qualifications ... DDR Design domain knowledge with good hold on DFI/DDR/LPDDR protocols * VSCode GitHub CoPilot or ...
$122K - $232K/yr
This position is not eligible for an intel immigration sponsorship. Preferred Qualifications ... DDR Design domain knowledge with good hold on DFI/DDR/LPDDR protocols * VSCode GitHub CoPilot or ...
$122K - $232K/yr
This position is not eligible for an intel immigration sponsorship. Preferred Qualifications ... DDR Design domain knowledge with good hold on DFI/DDR/LPDDR protocols * VSCode GitHub CoPilot or ...
$226K - $245K/yr
Join Intel as a Development Tools Software Engineer, where you will play a pivotal role in shaping ... Intel's technological advancement. In this critical position, you will architect, design, and ...
$226K - $245K/yr
Join Intel as a Development Tools Software Engineer, where you will play a pivotal role in shaping ... Intel's technological advancement. In this critical position, you will architect, design, and ...
Folsom, CA · On-site
$145K - $177K/yr
About the Role As a Senior SoC Design Verification Engineer , you will lead verification efforts for complex system-on-chip (SoC) designs that enable Intel's next generation of client computing and ...
Folsom, CA · On-site
$145K - $177K/yr
About the Role As a Senior SoC Design Verification Engineer , you will lead verification efforts for complex system-on-chip (SoC) designs that enable Intel's next generation of client computing and ...
Santa Clara, CA · On-site
$158K - $212K/yr
As a Software Enabling and Optimization Engineer, you will play a pivotal role in driving Intel ... Intel product design and enhancements. - Support product hardening and scalability to ensure ...
Santa Clara, CA · On-site
$158K - $212K/yr
As a Software Enabling and Optimization Engineer, you will play a pivotal role in driving Intel ... Intel product design and enhancements. - Support product hardening and scalability to ensure ...
As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high ... Your work will drive Intel's success in achieving power, performance, and area goals, empowering ...
As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high ... Your work will drive Intel's success in achieving power, performance, and area goals, empowering ...
Santa Clara, CA · On-site
$237K/yr
We are seeking a highly experienced and motivated Principal Analog Design Engineer to lead the ... The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable ...
Santa Clara, CA · On-site
$237K/yr
We are seeking a highly experienced and motivated Principal Analog Design Engineer to lead the ... The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable ...
Folsom, CA · On-site
$144K - $193K/yr
As a Software Enabling and Optimization Engineer, you will play a pivotal role in driving Intel ... Intel product design and enhancements. - Support product hardening and scalability to ensure ...
Folsom, CA · On-site
$144K - $193K/yr
As a Software Enabling and Optimization Engineer, you will play a pivotal role in driving Intel ... Intel product design and enhancements. - Support product hardening and scalability to ensure ...
Intel's Chandler, Arizona facility is constructing state-of-the-art fabrication facilities for ... We seek an experienced Senior Staff Collateral Design and DFM Engineer to join our MDCE team and ...
Intel's Chandler, Arizona facility is constructing state-of-the-art fabrication facilities for ... We seek an experienced Senior Staff Collateral Design and DFM Engineer to join our MDCE team and ...
Santa Clara, CA · On-site
$141K - $269K/yr
The Role and Impact Join Intel in shaping the future of technology. As an EDA Tools Hardware ... We are seeking an experienced EDA CAD / Tool Flow Development Engineer to develop and maintain ...
Santa Clara, CA · On-site
$141K - $269K/yr
The Role and Impact Join Intel in shaping the future of technology. As an EDA Tools Hardware ... We are seeking an experienced EDA CAD / Tool Flow Development Engineer to develop and maintain ...
Life at Intel: The Mask Metrology group at Intel Mask Operations is looking for an engineer who has ... software design Preferred Qualifications: * Interest in developing tools for engineers and ...
Life at Intel: The Mask Metrology group at Intel Mask Operations is looking for an engineer who has ... software design Preferred Qualifications: * Interest in developing tools for engineers and ...
Santa Clara, CA · On-site
$226K - $245K/yr
... Intel's technological advancement. In this critical position, you will architect, design, and ... software tools, flows, and methodologies for engineering and development processes • Collaborate ...
Santa Clara, CA · On-site
$226K - $245K/yr
... Intel's technological advancement. In this critical position, you will architect, design, and ... software tools, flows, and methodologies for engineering and development processes • Collaborate ...
Folsom, CA · On-site
$122K - $232K/yr
This position is not eligible for an intel immigration sponsorship. Preferred Qualifications ... DDR Design domain knowledge with good hold on DFI/DDR/LPDDR protocols * VSCode GitHub CoPilot or ...
Folsom, CA · On-site
$122K - $232K/yr
This position is not eligible for an intel immigration sponsorship. Preferred Qualifications ... DDR Design domain knowledge with good hold on DFI/DDR/LPDDR protocols * VSCode GitHub CoPilot or ...
Folsom, CA · On-site
$144K - $193K/yr
As a Software Enabling and Optimization Engineer, you will play a pivotal role in driving Intel ... Intel product design and enhancements. - Support product hardening and scalability to ensure ...
Folsom, CA · On-site
$144K - $193K/yr
As a Software Enabling and Optimization Engineer, you will play a pivotal role in driving Intel ... Intel product design and enhancements. - Support product hardening and scalability to ensure ...
$149K - $284K/yr
Designs, develops, tests, and debugs software tools, flows, and methodologies used in design ... Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while ...
$149K - $284K/yr
Designs, develops, tests, and debugs software tools, flows, and methodologies used in design ... Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while ...
$159K - $195K/yr
As a trusted domain expert, you will directly influence Intel's technical direction, mentor the ... design verification engineers, fostering a culture of continuous learning and improvement ...
$159K - $195K/yr
As a trusted domain expert, you will directly influence Intel's technical direction, mentor the ... design verification engineers, fostering a culture of continuous learning and improvement ...
Intel's Chandler, Arizona facility is constructing state-of-the-art fabrication facilities for ... We seek an experienced Senior Staff Collateral Design and DFM Engineer to join our MDCE team and ...
Intel's Chandler, Arizona facility is constructing state-of-the-art fabrication facilities for ... We seek an experienced Senior Staff Collateral Design and DFM Engineer to join our MDCE team and ...
Life at Intel: The Mask Metrology group at Intel Mask Operations is looking for an engineer who has ... software design Preferred Qualifications: * Interest in developing tools for engineers and ...
Life at Intel: The Mask Metrology group at Intel Mask Operations is looking for an engineer who has ... software design Preferred Qualifications: * Interest in developing tools for engineers and ...
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$122K - $232K/yr
Full-time
Medical, Retirement, PTO
Re-posted 21 days ago
8.7
Based on 147 frontline employees who took The Breakroom Quiz
19th of 159 rated electronics manufacturers
Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal and/or highspeed IPs required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods for mixed signal designs including analog behavior modeling and circuit simulation to write RTL and optimize mixed signal logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the IP block.
Qualifications:Minimum Qualifications:
2+ years of experience with the following technical skills:
This position is not eligible for an intel immigration sponsorship.
Preferred Qualifications:
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, FolsomAdditional Locations:US, California, San Jose, US, California, Santa ClaraPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Manufacturing
10,000+ Employees
Santa Clara, CA, US
1968