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60 Advantest Senior Asic Design Engineer Jobs Hiring Near You

... in Advantest 93000 tester is must * Skill in ATE architecture and Test Hardware Design and ... issues to the senior management. * Travel is required and able to travel domestically and ...

Job Overview Advantest Interconnect Solutions (AIS) has a senior A pplications Engineering position. Senior engineers are responsible for the design and development of ATE (automatic test equipment ...

Job Overview Advantest Interconnect Solutions (AIS) has a senior A pplications Engineering position. Senior engineers are responsible for the design and development of ATE (automatic test equipment ...

... Senior Applications Engineer to provide technical leadership and support for Advantest's V93000 ... Design and validate test solutions that align with customer business objectives. * Identify and ...

... Senior Applications Engineer to provide technical leadership and support for Advantest's V93000 ... Design and validate test solutions that align with customer business objectives. * Identify and ...

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Infographic showing various Senior Asic Design Engineer job openings at Advantest in the United States as of July 2026, with employment types broken down into 96% Full Time, 3% Part Time, and 1% Temporary. Highlights an 98% Physical, 1% Hybrid, and 1% Remote job distribution.
Senior ASIC Design Engineer DfT (m/f/d)

Senior ASIC Design Engineer DfT (m/f/d)

Advantest

Hall Summit, LA โ€ข On-site

Full-time

Posted 16 days ago


Job description

Join a global, highly skilled engineering team at the heart of Advantest's cutting edge IC test solutions. As a Digital ASIC Design Engineer, you will help create the key technologies that enable the next generation of semiconductor testing.
You will work on complex mixed signal ASICs used in Advantest's industry leading testers, taking digital modules and subsystems from first concept all the way to silicon in the final system, giving you true end to end ownership.
In this role, you will collaborate closely with system architects and design engineers. You will have a focus on generating test structures and memory BIST into existing circuity of IP blocks and the chip top level. You will use tools for pattern generation, keep power consumption under control, solve challenging technical problems, and deliver high quality results on schedule and at scale.
Job Duties & Responsibilities

  • Requirements gathering and elicitation for IP
  • Architecture development for CMOS IP designs
  • Design and RTL coding of digital and full-custom modules
  • Verification on module and chip level including test plan/cases generation.
  • Design for Test in existing IP and chip top level, implementation of memory BIST
  • Support for floor-planning and physical design
  • Test pattern generation
  • Collaboration with other functions
  • BS in Electrical Engineering/Physics/Computer Science or equivalent with over
    5 years' experience in Design for Test and BIST
  • Knowledge of digital, mixed signal, RF and power device test methodologies
  • Experience in Register Transfer Level (RTL) coding (Verilog and System Verilog)
  • Experience with standard simulation tools for digital designs
  • Ability to work in a fast paced, project oriented, team environment.
  • Positive attitude and excellent communication skills are a must.