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60 Voltus Jobs Hiring Near You

Apple

Gate-level SigEM/SEB/FIT CAD Engineer

Austin, TX

$150K - $277K/yr

Voltus, Voltus-Fi, RedHawk-SC, Totem Experience with analysis, optimization, or debugging of IR/IVD/EM issues on high performance, large-scale designs and silicon Familiarity with advanced packaging ...

Apolis

Physical Design Engineer

Santa Clara, CA · On-site

$159K - $164K/yr

... Voltus (EMIR) Good understanding of low-power design techniques and signoff methodologies. Preferred Qualifications Bachelor's or master's degree in electrical/Electronic Engineering. Experience in ...

Apple

Gate-level SigEM/SEB/FIT CAD Engineer

Austin, TX

$184K - $324K/yr

Voltus, Voltus-Fi, RedHawk-SC, Totem Hands-on experience with analysis, optimization, and debugging of IR/IVD/EM issues on high performance, large-scale designs and silicon Familiarity with advanced ...

Apple

Gate-level SigEM/SEB/FIT CAD Engineer

Austin, TX

$184K - $324K/yr

Voltus, Voltus-Fi, RedHawk-SC, Totem Hands-on experience with analysis, optimization, and debugging of IR/IVD/EM issues on high performance, large-scale designs and silicon Familiarity with advanced ...

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Contract Hardware Engineer Mid- #26-18016

N2S Global

San Jose, CA • On-site

$236K/yr

Contractor

Posted 18 days ago

Job description

Duration:12+ monthsDetails: What candidate will Be Doing:
  • Circuit Architecture & Design: Architect and design high-performance analog/mixed-signal building blocks (e.g., PLLs, ADCs/DACs, LDOs, Bandgaps, SerDes/PHY, Op-Amps).
What we are looking for:
  • Design Experience: 8–12 years of hands-on experience in analog IC design.
  • Circuit Architecture & Design: Architect and design high-performance analog/mixed-signal building blocks (e.g., PLLs, ADCs/DACs, LDOs, Bandgaps, SerDes/PHY, Op-Amps).
  • EDA exposure: Custom Design/Schematic: Cadence Virtuoso (ADE/Maestro). Simulation: Spectre, ClientICE, or CustomSim. Physical Verification: Mentor Calibre (DRC/LVS/PEX) or Synopsys IC Validator. Reliability/Sign-off: Experience with Voltus, RedHawk, or similar power/IR integrity tools.
  • Multi-Node Design: Translate and optimize designs across different process geometries, including transition strategies from Planar (e.g., 28nm) to FinFET (e.g., 16nm, 7nm...) nodes.
  • Simulation & Verification: Perform comprehensive pre-layout and post-layout simulations, including Monte Carlo, corner analysis, noise analysis, and reliability modeling (EM/IR/Aging/BTI/HCI).
  • Methodology: Drive best practices in analog design methodology, including the adoption of automated design tools and script-based verification (Python/SKILL/Tcl).

About US Tech Solutions: US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more about US Tech Solutions, please visit www.ustechsolutions.com.

US Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, colour, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

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