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Voltus

60 Voltus Jobs Hiring Near You

DRC, LVS, antenna, ERC, and tapeout readiness using industry-standard tools (e.g., Innovus, ICC2, Calibre, Voltus, RedHawk). * Contribute to and improve physical design automation infrastructure ...

Physical Design Engineer

San Jose, CA · On-site

$159K - $164K/yr

Physical Design Engineer Bay Area, CA Long term Contract F2F is required Good understanding of Cadence tools (Innovous, Quantus, Voltus). (Must) Deep knowledge about industry standards in Physical ...

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Physical Design Engineer

Phoenix, AZ

$135K - $139K/yr

Exp. in Block-level & Full-chip floor-planning & power grid planning,w/Python, TCL,or Perl progr., working w/EDA tools like DC/Genus, ICC2/Innovus, Primetime,Redhawk/Voltus or Calibre Additional Job ...

Physical Design Engineer

Phoenix, AZ · On-site

$135K - $139K/yr

Exp. in Block-level & Full-chip floor-planning & power grid planning,w/Python, TCL,or Perl progr., working w/EDA tools like DC/Genus, ICC2/Innovus, Primetime,Redhawk/Voltus or Calibre Additional Job ...

Physical Design Engineer

Phoenix, AZ · On-site

$135K - $139K/yr

Exp. in Block-level & Full-chip floor-planning & power grid planning,w/Python, TCL,or Perl progr., working w/EDA tools like DC/Genus, ICC2/Innovus, Primetime,Redhawk/Voltus or Calibre Additional Job ...

Experience with Voltus, RedHawk, or similar power/IR integrity tools * Multi-Node Design: Translate and optimize designs across different process geometries, including transition strategies from ...

Voltus, Voltus-Fi, RedHawk-SC, Totem Hands-on experience with analysis, optimization, and debugging of IR/IVD/EM issues on high performance, large-scale designs and silicon Familiarity with advanced ...

Physical Design Engineer

Phoenix, AZ · On-site

$135K - $139K/yr

Exp. in Block-level & Full-chip floor-planning & power grid planning,w/Python, TCL,or Perl progr., working w/EDA tools like DC/Genus, ICC2/Innovus, Primetime,Redhawk/Voltus or Calibre Additional Job ...

Voltus, Voltus-Fi, RedHawk-SC, Totem Experience with analysis, optimization, or debugging of IR/IVD/EM issues on high performance, large-scale designs and silicon Familiarity with advanced packaging ...

Experience with Voltus, RedHawk, or similar power/IR integrity tools * Multi-Node Design: Translate and optimize designs across different process geometries, including transition strategies from ...

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Showing results 1-20

$70 - $75/hr

Full-time

Posted 4 days ago


Job description

Job Description JOB: Staff CAD Engineer LOCATION: Austin,TX CAD/design methodology engineer with strong ASIC flow experience + low-power power analysis/signoff + EMIR, ideally supporting GPU/CPU/SoC programs. Must Have 6+ years CAD / design methodology / design enablement for GPU, CPU, or complex SoC Strong end-to-end ASIC flow knowledge: RTL synthesis physical design timing/power/signoff Hands-on low-power analysis / optimization / signoff PrimePower, PowerArtist, Joules, Empower, RTL Architect, or similar Hands-on EMIR RedHawk, Totem, Voltus, or equivalent CAD/EDA tools across Synopsys, Cadence, or Mentor/Siemens Automation/debugging of CAD flows and methodology issues