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60 Greenthumb Landscape Architect Jobs Hiring Near You

ChurnZero

Customer Education Architect

Washington, DC · Remote

$80K - $100K/yr

Customer Education Architect Overview ChurnZero is rethinking how customer enablement works. We are ... Parta.io * TechSmith Suite: Camtasia, Snagit, Audiate * Canva and PowerPoint (general graphics ...

ChurnZero

Customer Education Architect

Washington, DC · Remote

$80K - $100K/yr

Customer Education Architect Overview ChurnZero is rethinking how customer enablement works. We are ... Parta.io * TechSmith Suite: Camtasia, Snagit, Audiate * Canva and PowerPoint (general graphics ...

ChurnZero

Customer Education Architect

Washington, DC · On-site

$80K - $100K/yr

Customer Education Architect Overview ChurnZero is rethinking how customer enablement works. We are ... Parta.io * TechSmith Suite: Camtasia, Snagit, Audiate * Canva and PowerPoint (general graphics ...

Tech Digital Group

Data Architect

Raritan, NJ · On-site

$65.25 - $84/hr

... landscape, system integration and intelligent automation. * Capture architecture and design information and decisions using client-standard tools (Lean IX, SAXpress, Asset Management, Draw-IO, AMT ...

MICROVAST INC

SAP Architect

Houston, TX · On-site

Your job is to keep the SAP landscape documented and audit ready as the business changes it ... Experience with process documentation and diagramming tools (Visio, Draw.io, or equivalent) and ...

Tech Digital Group

Solution Architect

Raritan, NJ · On-site

$64.50 - $85/hr

... landscape, system integration and intelligent automation. * Capture architecture and design information and decisions using Client-standard tools (Lean IX, SAXpress, Asset Management, Draw-IO, AMT ...

Celersoft

... IO), Product Costing (CO-PC), and Profitability Analysis (CO-PA / Margin Analysis). Cross-Module ... hybrid landscapes. Communication: Outstanding verbal and written communication skills to deliver ...

Horace Mann

Domain Managing Architect - Cloud

Plano, TX · On-site

$62.50 - $79.75/hr

... landscapes. • Ability to define and govern enterprise architecture standards, patterns, reference ... Visio, draw.io). • Collaborate with business leaders, IT leadership, and engineering ...

Horace Mann

Domain Managing Architect - Cloud

Springfield, IL · On-site

$64.50 - $82/hr

... landscapes. * Ability to define and govern enterprise architecture standards, patterns, reference ... Expertise in creating architecture artifacts and diagrams (e.g., Visio, draw.io). * Collaborate ...

Slalom Consulting

General Information

Boston, MA · On-site

$77.50 - $97.50/hr

... io), Source to Pay, and Financial Services Operations (FSO). You will architect, propose, and lead ... business processes, technology landscape, and transformation goals, aligning ServiceNow ...

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FPGA DDR and IO Subsystem Architect

Altera Corporation

San Jose, CA • On-site

$200K - $286K/yr

Full-time

Re-posted 15 days ago

Job description

Job Details:
Job Description:
About Altera
Altera is a leading innovator in FPGA technology, delivering programmable solutions that power the world's data-centric applications-from cloud and communications infrastructure to automotive, industrial, and edge AI. Our mission is to enable customers to accelerate innovation through high-performance, power-efficient, and easy-to-use FPGA platforms. At Altera, you'll work alongside world-class engineers to architect next-generation silicon solutions that redefine performance, flexibility, and customer experience.
About the Role
As an FPGA DDR and IO Subsystem Architect, you will define and drive the architecture for next-generation high-speed external memory and general-purpose IO subsystems across Altera's FPGA product portfolio. You will play a pivotal role in shaping differentiated memory and IO capabilities that enable industry-leading performance, power efficiency, and usability.
This is a highly visible technical leadership role requiring deep expertise in DDR and high-speed IO standards, silicon architecture, and cross-functional collaboration from early concept through production.
Responsibilities
  • Develop the architecture for Altera's High-Speed External Memory Interfacing and General IO Silicon Subsystem.
  • Apply deep knowledge of memory and non-memory IO applications such as DDR5, LPDDR5, MIPI, LVDS, and ONFI, as well as the competitive landscape, to architect Altera's next-generation solutions.
  • Define subsystem-level specifications and detailed micro-architecture in collaboration with circuit design, PHY, controller, packaging, signal integrity, and system teams.
  • Own the solution lifecycle from early concept and feasibility analysis through silicon bring-up, validation, qualification, and production release.
  • Partner closely with the Altera Quartus software team to ensure best-in-class customer usability, performance tuning, configuration, and debug capabilities.
  • Drive architectural trade-off analysis across performance, power, area (PPA), cost, scalability, and reliability.
  • Lead technical reviews and provide guidance across RTL design, circuit design, verification, validation, packaging, and software teams to ensure architectural intent is realized in silicon.
  • Analyze competitive FPGA and ASIC IO/memory subsystem implementations to identify differentiation opportunities.
  • Engage with strategic customers and ecosystem partners to understand emerging requirements and influence future product roadmaps.

Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$200,400 - $286,000 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
Qualifications:
Minimum Qualifications
  • Bachelor's Degree (BE) or higher in Electrical Engineering.
  • 10+ years of hands-on experience in RTL design and ASIC design flows, including synthesis and static timing analysis (STA).
  • Strong working knowledge of Verilog, SystemVerilog, C++, and Python.
  • Deep understanding of the latest SDRAM technologies with hands-on experience in DDR4/DDR5 and/or LPDDR4/LPDDR5 controller, PHY, and subsystem design.
  • Experience architecting and delivering high-speed external memory subsystems in advanced semiconductor process nodes.
  • Experience in silicon architecture definition, micro-architecture development, and system-level trade-off analysis.
  • Experience driving cross-functional collaboration across RTL design, circuit design, verification, validation, packaging, and software teams.
  • Experience in signal integrity, power integrity, timing closure, and high-speed interface validation methodologies.
  • Knowledge of general IO standards (such as MIPI, LVDS, ONFI, or similar) is desired.

Preferred Qualifications
  • Master's or Ph.D. in Electrical Engineering or related discipline.
  • Experience with FPGA architectures and programmable IO subsystems.
  • Prior ownership of memory controller + PHY co-architecture and integration.
  • Experience collaborating with EDA/software teams to optimize tool flows, configuration, calibration, and debug.
  • Familiarity with advanced packaging technologies and multi-die integration.
  • Experience supporting silicon bring-up, lab characterization, and customer debug.
  • Strong communication and technical leadership skills with the ability to influence roadmap decisions.

Job Type:
Regular
Shift:
Shift 1 (United States of America)
Primary Location:
San Jose, California, United States
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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