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What is it like to work at Cook Group?

Cook Group is a privately-held company that values a collaborative and innovative work environment, prioritizing employee growth and well-being. The company operates through a decentralized structure, allowing its various business units, including medical device manufacturing and research, to maintain a high degree of autonomy and flexibility. Working at Cook Group may appeal to candidates seeking a dynamic and supportive work environment where they can contribute to the development of life-changing medical technologies.

What makes Cook Group an attractive place to work?

Cook Group is a leading medical device company known for its commitment to innovation and improving patient outcomes through its diverse portfolio of products and services. The company's workplace culture values collaboration, employee growth, and stability, offering a supportive environment with opportunities for professional development and advancement. As a result, Cook Group is an attractive place to work for individuals seeking a challenging and rewarding career in the medical device industry.

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Principal Collateral Device Engineer

Intel Corporation

Santa Clara, CA • On-site

Full-time

Medical, Retirement, PTO

Re-posted 15 days ago


Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

19th of 157 rated electronics manufacturers


Job description

Job Details:
Job Description:
Intel is transforming from an Integrated Device Manufacturer (IDM) to a leading foundry service provider, offering world-class manufacturing capabilities to customers worldwide. Our Manufacturing Development and Customer Engineering (MDCE) organization is at the forefront of this transformation, focusing on yield improvement, performance optimization, and exceptional customer service delivery.
We are seeking a Principal Collateral Device Engineer to join our team within MDCE. This role requires regular onsite presence to fulfill essential job responsibilities and will creates next generation device and interconnect technology by ensuring the process device performance for developing processes is world class, using deep understanding of device physics.
Key Responsibilities:
  • Demonstrated expertise in leading cross functional group in defining derivative architectures including Design rules, transistors and interconnects. Expertise in CMOS semiconductor device physics and test chip design for advanced transistor device architecture.
  • Experience in scribe line layout design and process monitoring structure development.
  • Proficiency in design rule development, validation, and waiver management processes.
  • Strong understanding of DTCO skills Including understanding of SRAM, Standard cells and be the key interface and bridge between Process Integration , Yield, Device and Design.
  • Strong skills in data analysis, scripting, and statistical techniques for test chip data interpretation.
  • Excellent technical problem-solving skills with ability to balance design rule compliance with customer flexibility needs.
  • Ability to work collaboratively in globally diverse, cross-disciplinary teams to develop innovative device collateral solutions.
  • Demonstrated experience with design of experiment (DOE) principles applied to device collateral optimization.
  • Proven track record of delivering device collateral solutions in a fast-paced manufacturing environment.
  • Desire to learn, lead, and influence cross-functional teams in collateral development and design rule optimization.

Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
  • Master's degree in Electrical Engineering, Physics, or related field
  • 15+ years of experience in CMOS device engineering with focus on test chip design and device collateral development

Preferred Qualifications:
  • Ph.D. degree in Electrical Engineering, Physics, or related field
  • 15+ years of experience in CMOS device engineering and collateral development
  • Hands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs
  • Experience with design rule checker (DRC) development and physical verification flows
  • Experience in High-Volume Manufacturing environment with focus on yield monitoring and process control structures
  • Knowledge of statistical process control (SPC) and advanced data analytics for device collateral optimization
  • Knowledge of mask generation including Boolean/OPC .

Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Santa Clara
Additional Locations:
US, Arizona, Phoenix, US, Oregon, Hillsboro
Business group:
Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $224,970.00-317,600.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968