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Work From Home Rtl Design Engineer Jobs in Arizona

The Jernigan Agency

WORK FROM HOME

Phoenix, AZ · On-site +1

$300 - $500/wk

We are looking for individuals interested in working from home, remotely, as life insurance sales representatives. We are hiring coachable individuals comfortable with a 100% commission based income ...

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Work From Home Rtl Design Engineer information

See Arizona salary details

$37.7K

$82.1K

$147.7K

How much do work from home rtl design engineer jobs pay per year?

As of Jun 23, 2026, the average yearly pay for work from home rtl design engineer in Arizona is $82,145.00, according to ZipRecruiter salary data. Most workers in this role earn between $63,400.00 and $91,800.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive in the Work From Home Rtl Design Engineer position, and why are they important?

A Work From Home RTL Design Engineer requires a thorough understanding of digital design, hardware description languages (such as Verilog or VHDL), and a relevant degree in electrical or computer engineering. Familiarity with industry-standard EDA tools like Synopsys, Cadence, or Mentor Graphics, and knowledge of design validation methodologies are commonly expected. Strong problem-solving abilities, effective communication skills, and self-motivation are crucial soft skills, particularly in a remote setting. These competencies ensure the engineer can deliver high-quality work, collaborate virtually with cross-functional teams, and meet project milestones in a distributed environment.

What is a Work From Home RTL Design Engineer job?

A Work From Home RTL (Register Transfer Level) Design Engineer is responsible for designing and implementing digital circuits using hardware description languages like Verilog or VHDL, all while working remotely. They develop RTL code for FPGA or ASIC designs, perform functional verification, and collaborate with hardware and software teams to ensure proper integration. This role requires strong knowledge of digital design principles, low-power design techniques, and simulation tools. Working remotely, engineers communicate via online tools, participate in virtual design reviews, and manage tasks independently while ensuring design quality and meeting project deadlines.

What are some typical challenges faced by Work From Home RTL Design Engineers, and how do companies support remote collaboration?

Remote RTL Design Engineers may face challenges such as limited access to on-site lab hardware, dependence on remote computing resources, and the need for clear communication across time zones. To address these, many companies provide secure VPN access, cloud-based EDA tool licenses, and regular virtual team meetings to ensure seamless project progress. You will often collaborate with verification, software, and hardware teams via video calls, shared documentation platforms, and version control systems. Structured onboarding, virtual mentorship programs, and flexible work hours are additional ways organizations support remote RTL designers. Adapting to these systems helps maintain productivity and fosters a collaborative team environment despite geographical distances.

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Work From Home Rtl Design Engineer jobs near you

Principal Digital Design Engineer

PowerLattice

Chandler, AZ • On-site, Remote

$200K - $250K/yr

Full-time

Medical, Dental, Vision, Retirement

Posted 22 days ago

Job description

Hybrid requiring 3 days a week onsite in the office
Reports To: Head of Engineering
About Us
PowerLattice is a well-funded semiconductor start-up company backed by well-known large Silicon Valley VCs. The company is working on the industry's groundbreaking chiplet solution for a fundamental shift in how high-performance chips get powered, paving the way for the next generation of AI and advanced computing.
About the Role
We are seeking a highly skilled and hands-on Principal Digital Design Engineer to drive the microarchitecture, design, and implementation of complex digital systems and SoC components. This role combines deep technical contribution with team leadership, requiring active involvement from microarchitecture definition through RTL development and into back-end implementation and silicon bring-up.
Key Responsibilities
  • Architecture & Hands-On Design
  • Define microarchitecture for complex digital blocks and subsystems
  • Actively contribute to RTL development for key components
  • Drive design tradeoffs across performance, power, area (PPA), and testability
  • RTL Development & Integration
  • Write, review, and integrate high-quality RTL
  • Lead block- and chip-level integration, resolving interface and system issues
  • Ensure designs are clean for lint, CDC/RDC, and synthesis
  • Back-End & Implementation Ownership
  • Ensure RTL is optimized for synthesis, timing, and physical design
  • Work on scan insertion, test architecture, and coverage closure
  • Perform, review and debug logic equivalence checking (LEC) results between RTL and netlists
  • Define and validate timing constraints (SDC) and complete timing closure
  • Drive and implement timing and functional ECOs as needed
  • Design Quality & Signoff
  • Drive signoff readiness including lint, CDC/RDC, synthesis, LEC, and timing checks
  • Ensure designs meet functional, timing, power, and test requirements
  • Support silicon bring-up, debug, and root-cause analysis
  • Cross-Functional Collaboration
  • Work closely with verification, physical design, DFT, and firmware teams
  • Align design decisions with verification plans and implementation
    Constraints
  • Act as the technical bridge between front-end and back-end teams

Qualifications
This is a Hybrid role requiring 3 days a week onsite at our HQ's in Vancouver, WA (Greater Portland Area) or Chandler, AZ. While we are primarily seeking candidates in HQ-Vancouer and Chandler, remote flexibility may be considered for exceptional candidates in Silicon Valley, CA.
  • Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field
  • 10+ years of experience in digital design with significant hands-on RTL development
  • Proven track record of delivering complex SoC or subsystem designs to tapeout
  • Strong expertise in:
    • RTL design and microarchitecture
    • SoC integration and standard interfaces
  • Hands-on experience with back-end flows, including:
    • Scan insertion and DFT (scan, MBIST, test coverage)
    • Logic equivalence checking (LEC)
    • Static timing analysis (STA) and timing closure
    • Timing constraint development and debug (SDC)
  • Solid understanding of:
    • Clocking, resets, CDC/RDC, and low-power design
    • Synthesis and physical design implications
  • Experience with industry-standard EDA tools (Synopsys, Cadence)
  • Experience with low-power methodologies (UPF/CPF)
  • Strong debugging and problem-solving skills

Preferred Qualifications
  • Familiarity with advanced technology nodes and implementation challenges
  • Experience with formal verification techniques
  • Experience with silicon bring-up and post-silicon debug

Compensation & Benefits
Anticipated annual base salary for Member of Technical Staff: $200,000 - $250,000
  • Stock option grant
  • Comprehensive benefits package including health, dental, vision, and 401(k)

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