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Wireless Digital Communication Engineer Jobs (NOW HIRING)

L3HHCM20

Lead, Software Engineer - FPGA

Salt Lake City, UT

$124K - $160K/yr

FPGA EW Design Engineer Job Code: 41806 Job Location: Salt lake City Job Schedule: 9/80, employees ... Ideal candidates bring experience in EW, wireless communications, modems, and/or digital signal ...

Apple

Digital Hardware Engineer

Sunnyvale, CA · On-site

Description The digital hardware design engineer will closely work with internal hardware and ... of wireless or cellular modem chipsets Strong communication skills coupled with a proactive ...

Apple

Digital Hardware Engineer

Sunnyvale, CA · On-site

Description The digital hardware design engineer will closely work with internal hardware and ... of wireless or cellular modem chipsets Strong communication skills coupled with a proactive ...

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Wireless Digital Communication Engineer information

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How much do wireless digital communication engineer jobs pay per year?

As of Sep 11, 2026, the average yearly pay for wireless digital communication engineer in the United States is $170,719.00, according to ZipRecruiter salary data. Most workers in this role earn between $150,000.00 and $191,000.00 per year, depending on experience, location, and employer.

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Lead, Software Engineer - FPGA

Salt Lake City, UT

L3HHCM20
See more jobs at L3HHCM20external

$124K - $160K/yr

Full-time

Posted 28 days ago

Job description

Job Title: FPGA EW Design Engineer

Job Code: 41806

Job Location: Salt lake City

Job Schedule: 9/80, employees work 9 out of 14 days- totaling 80 hours worked- and have every other Friday off

 

We are seeking an experienced FPGA Design Engineer to help develop advanced electronic warfare (EW) and wireless digital communications systems. Ideal candidates bring experience in EW, wireless communications, modems, and/or digital signal processing (DSP). You will contribute across the full design lifecycle, including proposals, requirements definition, RTL development, simulation, synthesis, place-and-route, verification and test, system integration, and field support. This role offers challenging technical work within a collaborative team of talented engineers and opportunities to work independently while leading small teams of technical contributors. Located in Salt Lake City, this position also offers access to exceptional year-round outdoor recreation and cultural experiences, supported by L3Harris's commitment to work-life balance.

Candidates with experience or education in one or more of the following areas are encouraged to apply:

  • Electronic warfare (EW)
  • Signal detection, classification, and identification
  • Radar systems and signal processing
  • Advanced digital signal processing (DSP) techniques
  • Digital modulation and demodulation
  • Forward error correction (FEC)
  • Machine learning
  • FPGA verification using simulation and unit testing
  • Experience developing in VHDL (preferred) or Verilog

Minimum Qualifications:

  • Bachelor's Degree and minimum 9 years of prior relevant experience. Graduate Degree and a minimum of 7 years of prior related experience. In lieu of a degree, minimum of 13 years of prior related experience
  • Current DOD clearance or the ability to aquire one.

Preferred Qualifications:

  • Master's degree in computer science, computer engineering, software engineering, or electrical engineering
  • Experience leading small engineering teams or technical contributors
  • Experience developing electronic support (ES) and/or electronic attack (EA) signal-processing capabilities
  • Experience implementing complex modem and/or DSP algorithms in FPGA-based programmable logic; comparable ASIC design experience is also applicable
  • Experience implementing industry-standard interfaces, such as 10/100/1000 Ethernet, SPI, UART, SDRAM, DDR3, JESD, and PCIe
  • Experience with FPGA simulation, synthesis, and implementation tools, such as ModelSim, Synplify, AMD Xilinx Vivado/ISE, and/or Intel Quartus
  • Experience with high-speed serial FPGA interfaces operating at 3 Gbps or greater
  • Experience achieving timing closure in large FPGA designs
  • Experience with high-level synthesis (HLS)
  • Hands-on laboratory debug experience using signal generators, digital oscilloscopes, logic analyzers, bit-error-rate testers (BERTs), and other advanced measurement equipment
  • Familiarity with Git source control
  • Familiarity with C, C++, C#, MATLAB, and/or Simulink

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