FPGA / VLSI Engineer
$120K - $220K/yr
Design and implement RTL using SystemVerilog with consideration for timing, power, and area ... This means that there will be times when extra hours, including nights and weekends, may be needed ...
Quick apply
$120K - $220K/yr
Design and implement RTL using SystemVerilog with consideration for timing, power, and area ... This means that there will be times when extra hours, including nights and weekends, may be needed ...
Quick apply
$120K - $220K/yr
Design and implement RTL using SystemVerilog with consideration for timing, power, and area ... This means that there will be times when extra hours, including nights and weekends, may be needed ...
Saratoga, CA · On-site
$120K - $220K/yr
Medical
PTO
Design and implement RTL using SystemVerilog with consideration for timing, power, and area Perform ... This means that there will be times when extra hours, including nights and weekends, may be needed ...
Saratoga, CA · On-site
$120K - $220K/yr
Medical
PTO
Design and implement RTL using SystemVerilog with consideration for timing, power, and area Perform ... This means that there will be times when extra hours, including nights and weekends, may be needed ...
Saratoga, CA · On-site
$120K - $220K/yr
Medical
PTO
This role focuses on RTL design, FPGA prototyping, and system integration, working closely with ... This means that there will be times when extra hours, including nights and weekends, may be needed ...
Saratoga, CA · On-site
$120K - $220K/yr
Medical
PTO
This role focuses on RTL design, FPGA prototyping, and system integration, working closely with ... This means that there will be times when extra hours, including nights and weekends, may be needed ...
Saratoga, CA · On-site
$120K - $220K/yr
Medical
PTO
Design and implement RTL using SystemVerilog with consideration for timing, power, and area Perform ... This means that there will be times when extra hours, including nights and weekends, may be needed ...
Saratoga, CA · On-site
$120K - $220K/yr
Medical
PTO
Design and implement RTL using SystemVerilog with consideration for timing, power, and area Perform ... This means that there will be times when extra hours, including nights and weekends, may be needed ...
Santa Clara, UT · On-site
$45K - $121K/yr
Medical
Dental
PTO
L11 PDE JD: (Graveyard Shift) What you will be doing: • Working night, swing and weekend shifts ... VLSI Board Design. Experience: 3-5 Years. The expected compensation for this role ranges from $45 ...
Santa Clara, UT · On-site
$45K - $121K/yr
Medical
Dental
PTO
L11 PDE JD: (Graveyard Shift) What you will be doing: • Working night, swing and weekend shifts ... VLSI Board Design. Experience: 3-5 Years. The expected compensation for this role ranges from $45 ...
Santa Clara, UT · On-site
$45K - $121K/yr
Medical
Dental
PTO
... swing and weekend shifts to support extended factory operations hours • Reviewing build ... VLSI Board Design. Experience: 3-5 Years. The expected compensation for this role ranges from $45 ...
Santa Clara, UT · On-site
$45K - $121K/yr
Medical
Dental
PTO
... swing and weekend shifts to support extended factory operations hours • Reviewing build ... VLSI Board Design. Experience: 3-5 Years. The expected compensation for this role ranges from $45 ...
Santa Clara, UT · On-site
$45K - $121K/yr
Medical
Dental
PTO
JD • Working Swing and weekend shifts to support extended factory operations hours • Reviewing ... VLSI Board Design. Experience: 3-5 Years. The expected compensation for this role ranges from $45 ...
New
Santa Clara, UT · On-site
$45K - $121K/yr
Medical
Dental
PTO
JD • Working Swing and weekend shifts to support extended factory operations hours • Reviewing ... VLSI Board Design. Experience: 3-5 Years. The expected compensation for this role ranges from $45 ...
New
$95K - $99.2K
0% of jobs
$99.2K - $103.5K
0% of jobs
$103.5K - $107.7K
0% of jobs
$107.7K - $111.9K
0% of jobs
$111.9K - $116.1K
0% of jobs
$116.1K - $120.4K
0% of jobs
$120.4K - $124.6K
0% of jobs
$124.6K - $128.8K
0% of jobs
$128.8K - $133K
1% of jobs
$135.4K is the 25th percentile. Wages below this are outliers.
$133K - $137.3K
43% of jobs
The median wage is $137.7K / yr.
$137.3K - $141.5K
56% of jobs
$95K
$141.5K
The most popular types of Vlsi Design jobs are:
$120K - $220K/yr
Full-time
Re-posted 12 days ago
• Design and implement RTL using SystemVerilog with consideration for timing, power, and area
• Perform FPGA prototyping, validation, and hardware bring-up for digital designs
• Develop and execute simulation and debugging strategies at block and subsystem levels
• Contribute to SoC-level integration, including interfacing with processors, memory, and peripherals
• Analyze and resolve timing issues, including setup/hold violations and basic clock domain crossing concerns
• Collaborate with verification, ASIC, and software teams to ensure functional correctness and performance
• Participate in design reviews and contribute to improving design quality and best practices
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