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Wafer Level Test Engineer Jobs (NOW HIRING)

$81K - $108K/yr

Senior Wafer Test Hardware Engineer, Raxium Google Fremont, CA, USA Mid Experience driving progress ... Drive the specification process for a parallel wafer-level test tool, coordinating with internal ...

$83K - $112K/yr

Analyze wafer-level parametric data, process control monitor structures, and device electrical ... test equipment and electrical measurement systems. * Programming experience in Python, C/C++, Perl ...

The RF Test Engineer I is responsible for characterizing, testing, and analyzing RF and microwave ... Perform wafer-level characterization and device validation. * Set up and maintain automated ...

The RF Test Engineer I is responsible for characterizing, testing, and analyzing RF and microwave ... Perform wafer-level characterization and device validation. * Set up and maintain automated ...

Job Title- Mid-Level Test Engineer Project Location - Hybrid in Stafford, Virginia Duration- 6+ months contract There are three rounds in this process - Phone screen, followed by two video interviews ...

Job Title- Mid-Level Test Engineer Project Location - Stafford, VA (Hybrid) Duration- 6+ months contract to hire Candidates must be a U.S. Citizen with Active Secret Clearance and will need to ...

Sr Test Engineer

San Jose, CA · On-site

$115K - $150K/yr

Build test infrastructure for wafer-level and package-level RF-MEMS testing, including probe ... Collaborate cross-functionally with RF design, MEMS design, process engineering, reliability, and ...

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Wafer Level Test Engineer information

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$11K

$109.6K

$183.5K

How much do wafer level test engineer jobs pay per year?

As of Sep 12, 2026, the average yearly pay for wafer level test engineer in the United States is $109,565.00, according to ZipRecruiter salary data. Most workers in this role earn between $80,000.00 and $143,000.00 per year, depending on experience, location, and employer.

What is a wafer level test engineer?

Wafer level test engineers are professionals who specialize in testing semiconductor wafers before they are cut into individual chips. They design, implement, and maintain testing procedures and equipment to evaluate the electrical performance and quality of integrated circuits at the wafer stage. Their work ensures that only functional chips proceed to the packaging stage, improving yield and reducing costs. Wafer level test engineers often collaborate with design, process, and manufacturing teams to optimize test coverage and efficiency.

What are the key skills and qualifications needed to thrive as a wafer level test engineer?

To thrive as a Wafer Level Test Engineer, you need a solid background in electrical engineering, semiconductor device physics, and experience with wafer test methodologies, typically supported by a relevant engineering degree. Proficiency in automated test equipment (ATE) such as Advantest or Teradyne, data analysis tools like JMP, and programming languages such as Python or C++ is essential. Strong problem-solving skills, attention to detail, and effective communication help you collaborate with cross-functional teams and address complex testing issues. These skills ensure accurate device characterization, efficient yield analysis, and overall product quality in the semiconductor manufacturing process.

What are some common challenges faced by wafer level test engineers, and how can they be addressed?

Wafer Level Test Engineers often encounter challenges such as managing high test throughput while maintaining accuracy, troubleshooting complex yield issues, and adapting to rapidly evolving semiconductor technologies. Addressing these challenges typically involves collaborating closely with process engineers, leveraging advanced automated test equipment, and continually updating one’s knowledge of new test methodologies. Effective communication and proactive problem-solving are essential to ensure smooth handoffs between design, manufacturing, and quality assurance teams.

What is the difference between Wafer Level Test Engineer vs Test Engineer?

AspectWafer Level Test EngineerTest Engineer
CredentialsTypically requires a degree in Electrical Engineering, Electronics, or related fieldsSimilar educational background, often with additional certifications in testing or quality assurance
Work EnvironmentWorks primarily in semiconductor fabrication and testing labs, focusing on wafer testing processesWorks in various industries including electronics, manufacturing, and product testing environments
Industry UsageCommonly employed in semiconductor and integrated circuit manufacturingUsed across multiple industries involving product testing and quality control

The main difference between a Wafer Level Test Engineer and a Test Engineer lies in their focus areas. Wafer Level Test Engineers specialize in testing semiconductor wafers during manufacturing, while Test Engineers may work on testing finished products across various industries. Both roles require similar technical skills and educational backgrounds, but their work environments and specific responsibilities differ significantly.

What are popular job titles related to Wafer Level Test Engineer jobs?

For Wafer Level Test Engineer jobs, the most frequently searched job titles are:

Infographic showing various Wafer Level Test Engineer job openings in the United States as of September 2026, with employment types broken down into 1% As Needed, 84% Full Time, 12% Part Time, 2% Contract, and 1% Nights. Highlights an 90% Physical, 1% Hybrid, and 9% Remote job distribution, with an average salary of $109,565 per year, or $52.7 per hour.

Senior Wafer Test Hardware Engineer, Raxium

On-site

Google Inc.
Software Development • 10K+ employees

$81K - $108K/yr

Other

Posted 4 days ago


Google rating

8.8

Company rating: 8.8 out of 10

Based on 103 frontline employees who took The Breakroom Quiz


Job description

Senior Wafer Test Hardware Engineer, Raxium

Google Fremont, CA, USA

Mid

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a specialized field (e.g., Optics, Sensors, Audio/DSP, etc.), or equivalent practical experience.
  • 5 years of experience in writing semiconductor functional tests, including register-level writes/reads and validation on production data.
  • 2 years proven experience with wafer-level probe technologies, including troubleshooting and failure analysis.
  • Experience validating hardware and software paths, including step-by-step component validation (e.g., verifying pin-to-pad contact and communication).
Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering, Physics, or a related field (e.g., Optics, Sensors, Audio/DSP).
  • Experience with reliability hardware bring-up and qualification.
  • Experience driving hardware specifications with external equipment vendors.
  • Experience with data analysis and visualization tools such as JMP, Python, or SQL.
  • Proficiency in structuring semiconductor test data streams, automating data ingestion and designing data visualizations or dashboards for operational monitoring.
  • Ability to lead technical projects autonomously and drive alignment across teams (Hardware, Silicon design, Data/IS, and Manufacturing).
About the job

Google's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets Google's standards of quality and reliability.

Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $159000 - $230000 (USD) + 15% bonus target + equity + benefits Learn more about benefits at Google .

  • Drive the specification process for a parallel wafer-level test tool, coordinating with internal teams on pad accommodations and initial bring-up plans.
  • Define and execute the hardware/software validation path, verifying individual vendor components (such as single-die verification or pin-to-pad communication) independently from the complete solution.
  • Define input and output data streams with vendors, and coordinate test and information systems (IS) infrastructure to manage and transfer massive die-level datasets.
  • Define the operational flow, integrate the reliability tool with the manufacturing execution system (MES), and establish clear standard operating procedures (SOPs).

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.

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