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Wafer Level Test Engineer Jobs (NOW HIRING)

Advantest

Lead Application Engineer

San Jose, CA · On-site

Own wafer-level (die-level) test program development, including silicon bring-up, characterization ... Collaborate closely with R&D, COE, and global engineering teams to develop next-generation wafer ...

skywater

Electrical Test Engineer

Austin, TX · On-site

Engineer will also be responsible for wafer level reliability (WLR) which tested similarly on ... Wafer level test program, conditions and capabilities * Product design, usage, and functionality

Advantest

Lead Application Engineer

San Jose, CA · On-site

Own wafer-level (die-level) test program development, including silicon bring-up, characterization ... Collaborate closely with R&D, COE, and global engineering teams to develop next-generation wafer ...

nEye.ai

Photonics Test Technician

Santa Clara, CA · On-site

$45 - $55/hr

You will be responsible for running wafer-level tests and operating advanced metrology systems, but ... Proactively flag irregularities to engineers, providing clear observations and context

Socket.dev

Principal Fab Test Engineer

Fort Collins, CO · On-site

The tool groups consist of replicated, custom, semi-custom, or purchased wafer level probers and ... As a WSD Fab Test Unit Process Engineer (TUPE), you will have a mix of both tactical and strategic ...

nEye.ai

Photonics Test Technician

Santa Clara, CA · On-site

$45 - $55/hr

You will be responsible for running wafer-level tests and operating advanced metrology systems, but ... Proactively flag irregularities to engineers, providing clear observations and context

nEye.ai

Photonics Test Technician

Santa Clara, CA · On-site

$45 - $55/hr

You will be responsible for running wafer-level tests and operating advanced metrology systems, but ... Proactively flag irregularities to engineers, providing clear observations and context

nEye Systems, Inc.

$45 - $55/hr

You will be responsible for running wafer-level tests and operating advanced metrology systems, but ... Proactively flag irregularities to engineers, providing clear observations and context

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All JobsWafer Level Test Engineer Jobs

Wafer Level Test Engineer information

See salary details

$11K

$109.6K

$183.5K

How much do wafer level test engineer jobs pay per year?

As of Sep 12, 2026, the average yearly pay for wafer level test engineer in the United States is $109,565.00, according to ZipRecruiter salary data. Most workers in this role earn between $80,000.00 and $143,000.00 per year, depending on experience, location, and employer.

What is a wafer level test engineer?

Wafer level test engineers are professionals who specialize in testing semiconductor wafers before they are cut into individual chips. They design, implement, and maintain testing procedures and equipment to evaluate the electrical performance and quality of integrated circuits at the wafer stage. Their work ensures that only functional chips proceed to the packaging stage, improving yield and reducing costs. Wafer level test engineers often collaborate with design, process, and manufacturing teams to optimize test coverage and efficiency.

What are the key skills and qualifications needed to thrive as a wafer level test engineer?

To thrive as a Wafer Level Test Engineer, you need a solid background in electrical engineering, semiconductor device physics, and experience with wafer test methodologies, typically supported by a relevant engineering degree. Proficiency in automated test equipment (ATE) such as Advantest or Teradyne, data analysis tools like JMP, and programming languages such as Python or C++ is essential. Strong problem-solving skills, attention to detail, and effective communication help you collaborate with cross-functional teams and address complex testing issues. These skills ensure accurate device characterization, efficient yield analysis, and overall product quality in the semiconductor manufacturing process.

What are some common challenges faced by wafer level test engineers, and how can they be addressed?

Wafer Level Test Engineers often encounter challenges such as managing high test throughput while maintaining accuracy, troubleshooting complex yield issues, and adapting to rapidly evolving semiconductor technologies. Addressing these challenges typically involves collaborating closely with process engineers, leveraging advanced automated test equipment, and continually updating one’s knowledge of new test methodologies. Effective communication and proactive problem-solving are essential to ensure smooth handoffs between design, manufacturing, and quality assurance teams.

What is the difference between Wafer Level Test Engineer vs Test Engineer?

AspectWafer Level Test EngineerTest Engineer
CredentialsTypically requires a degree in Electrical Engineering, Electronics, or related fieldsSimilar educational background, often with additional certifications in testing or quality assurance
Work EnvironmentWorks primarily in semiconductor fabrication and testing labs, focusing on wafer testing processesWorks in various industries including electronics, manufacturing, and product testing environments
Industry UsageCommonly employed in semiconductor and integrated circuit manufacturingUsed across multiple industries involving product testing and quality control

The main difference between a Wafer Level Test Engineer and a Test Engineer lies in their focus areas. Wafer Level Test Engineers specialize in testing semiconductor wafers during manufacturing, while Test Engineers may work on testing finished products across various industries. Both roles require similar technical skills and educational backgrounds, but their work environments and specific responsibilities differ significantly.

What are popular job titles related to Wafer Level Test Engineer jobs?

For Wafer Level Test Engineer jobs, the most frequently searched job titles are:

Infographic showing various Wafer Level Test Engineer job openings in the United States as of September 2026, with employment types broken down into 1% As Needed, 84% Full Time, 12% Part Time, 2% Contract, and 1% Nights. Highlights an 90% Physical, 1% Hybrid, and 9% Remote job distribution, with an average salary of $109,565 per year, or $52.7 per hour.

Senior Principal Photonics Test Engineer

San Jose, CA • On-site

Astera Labs
Semiconductor and Electronic Component Manufacturing • 11 - 50 employees
Learn more about Astera Labsexternal

$185K - $240K/yr

Full-time

Re-posted 25 days ago

Key responsibilities

  • Define and implement optical test architectures and test flows across various testing levels.

  • Execute characterization and qualification testing of optical components and assemblies.

  • Develop and automate optical test procedures and analyze test data to identify trends and failure modes.

Job description

  • Job Summary 

    We are seeking a highly technical and hands-on Senior Principal Photonics Test Engineer to serve as the technical authority for photonics test engineering across our product portfolio. This role will define end-to-end test architectures and drive advanced test development for silicon photonics devices, subsystems, and optical modules from early R&D through high-volume manufacturing. 

    The ideal candidate brings deep expertise in silicon photonics test methodologies, strong system-level thinking, and a proven ability to solve complex yield and performance challenges while building scalable, automated test solutions. 

    Key Responsibilities 

    • Define and own the end-to-end test architecture and test roadmap including wafer-level testing, package-level validation, optical engine and module characterization, as well as production and reliability testing. 
    • Lead the development of advanced wafer probe and package-level test solutions for silicon photonics devices and subsystems. 
    • Architect and implement automated test flows for engineering characterization, validation, and production. 
    • Design, develop, and implement optical test plans and procedures for co-packaged optics modules, including silicon photonics engines, laser sources, photodetectors, and optical fiber connectors. 
    • Debug and resolve yield issues and critical technical challenges, including electrical/optical performance failures, process & test induced variations. 
    • Develop and drive the hardware and software roadmap for next-generation optical test systems. 
    • Collaborate across cross-functional organizations such as silicon and photonics design teams, packaging, validation, reliability and qualification teams. 
    • Define and implement test and yield analytics frameworks to accelerate yield learning and root cause identification. 
    • Provide deep technical input in Design-for-Test (DfT) and product development reviews.  
    • Define test specifications, acceptance criteria, and pass/fail limits based on IEEE, OIF, and internal standards 

    Required Qualifications 

    • MS or PhD in Electrical Engineering, Optics, Physics, Semiconductor Engineering, or a related field.  
    • 10+ years of experience in optical testing, photonic device characterization, or optical transceiver module test. 
    • Strong understanding of silicon photonics devices (modulators, photodetectors, multiplexers, grating couplers, edge couplers), optical probing and fiber coupling, Electro-Optical (EO) characterization, high-speed optical testing and BER measurement.  
    • Proven experience leading development of wafer-level and package-level optical test systems.  
    • Programming skills in Python, MATLAB, LabVIEW, or C/C++ for test automation 
    • Knowledge of optical communication standards (IEEE 802.3, OIF-CEI, CMIS) 
    • Familiarity with statistical analysis methods and data visualization tools. Strong experience debugging yield issues and complex system-level problems.  
    • Excellent collaboration and communication skills, with the ability to influence across engineering disciplines. 

    Preferred Qualifications 

    • Experience specifically with co-packaged optics or on-board optics architectures. 
    • Knowledge of 2.5D/3D packaging technologies (interposers, chiplets, UCIe etc.). 
    • Experience with external laser source (ELS) integration and characterization. 
    • Experience with ATE platforms and custom photonics test setups. 
    • Experience in transitioning test processes from lab/prototype to high-volume manufacturing (HVM) 
     

Salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

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