ZipRecruiter

Log In

1

Vlsi Verification Integration Engineer Jobs (NOW HIRING)

Retym

DFT Tech Lead

Austin, TX · On-site

As a DFT Tech Lead you will work closely with all other design teams - backend, vlsi, verification ... Master's degree in Electrical Engineering. * Experience in IP integration (memories, Test ...

9 Mothers Corporation

Integration Engineer

Manor, TX · On-site

$112K - $150K/yr

Integration Engineer About 9 Mothers The modern battlefield has changed. Cheap, autonomous suicide ... verify correctness, timing, and reliability of data exchange between systems before and during ...

9 Mothers

Integration Engineer

Austin, TX · On-site

$103K - $138K/yr

Integration Engineer About 9 Mothers The modern battlefield has changed. Cheap, autonomous suicide ... verify correctness, timing, and reliability of data exchange between systems before and during ...

Intel Corporation

Conducts verification and signoff including formal equivalence verification, static timing analysis ... Logic Design, VLSI/ASIC Design, Computer Architecture Current Industry Experience in one or more ...

BIGDATAAPPTECH LLC

FPGA/VLSI engineer

California City, CA · On-site

$150K - $207K/yr

This role focuses on RTL design, FPGA prototyping, and system integration, working closely with ... with verification, ASIC, and software teams to ensure functional correctness and performance ...

Advanced Micro Devices

Understanding of VLSI design flow, from RTL through Physical Design and GDSII. * Familiarity with ... Knowledge of UVM/OVM verification, simulation environments, and debugging. * Understanding of FPGA ...

JANUS Research Group

$110K - $120K/yr

... verify, before applying, that you meet the minimum requirements of the position. Target salary ... JANUS Research Group is seeking a Senior Integration Engineer at Buckley Space Force Base to ...

Etech Hi

ASIC / VLSI Engineers

Milpitas, CA · On-site

Design Verification Engineer Compensation up to $225K DOE + strong benefits + long-term project stability. What You Need (All Roles) * 8+ years of pre-silicon ASIC / VLSI experience * Strong ...

Prosum Inc.

Systems Integration Engineer

Phoenix, AZ · On-site

$205K/yr

System Integration Engineer Our client is seeking a System Integration Engineer for a direct hire ... Verify system functionality and ensure successful integration with customer manufacturing ...

Steampunk

Integration Engineer

Mclean, VA · On-site

$100K - $160K/yr

As an Integration Engineer, you will work with our growing DevSecOps practice developing APIs and ... Steampunk participates in the E-Verify program.

previous page

Showing results 41-60

All JobsVlsi Verification Integration Engineer Jobs

Vlsi Verification Integration Engineer information

See salary details

$80K

$142.6K

$203.5K

How much do vlsi verification integration engineer jobs pay per year?

As of Sep 10, 2026, the average yearly pay for vlsi verification integration engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What are popular job titles related to Vlsi Verification Integration Engineer jobs?

For Vlsi Verification Integration Engineer jobs, the most frequently searched job titles are:

Infographic showing various Vlsi Verification Integration Engineer job openings in the United States as of August 2026, with employment types broken down into 92% Full Time, 2% Part Time, and 6% Contract. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.

DFT Tech Lead

Austin, TX • On-site

Retym
See more jobs at Retymexternal

Full-time

Re-posted 29 days ago

Job description

Description
We are looking for a talented and experienced DFT Tech Lead.
As a DFT Tech Lead you will work closely with all other design teams - backend, vlsi, verification and analog, fully responsible for defining, implementing, and deploying advanced design-for-test (DFT) methodologies for highly complex digital and mixed-signal chips. You will define silicon test strategies, DFT/DFD architecture, and create DFT and Debug specifications for complex next generation SoCs.
Requirements
Minimum qualifications:
  • 8+ Experience in DFT specification definition, architecture, insertion, and analysis in designs
  • Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG-related issues
  • Experience in fault modeling

Preferred qualifications:
  • Master's degree in Electrical Engineering.
  • Experience in IP integration (memories, Test controllers, TAP, MBIST).
  • Experience using EDA Test tools like Design/Fusion Compiler, DFT Max, SpyGlass, Modus, Tessent, and TestKompress.
  • Experience and understanding of ASIC DFT, synthesis, simulation and verification flow.
  • Excellent attention to detail organizational, problem-solving, and communication skills.

Responsibilities:
  • Create SoC DFT strategy and architecture (ATPG/DFT/MBIST)
  • Work on hierarchical design
  • Debug all Design Rule checks, apply design fixes to achieve high test quality
  • Insert all DFT logic - boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
  • Insert and hook up MBIST logic.
  • Define test plan for special analog IPs and implement.
  • Document DFT architecture and test sequences, including boot-up sequence associated with test pins.

Apply