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Vlsi Testing Jobs in California (NOW HIRING)

Analog Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

... testing and validation, • VLSI circuit and system design using Verilog, • Architecture design space exploration, • Spectrum Analyzer. Annual base salary for this role in California, US is ...

Analog Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

... testing and validation, • VLSI circuit and system design using Verilog, • Architecture design space exploration, • Spectrum Analyzer. Annual base salary for this role in California, US is ...

Post-tapeout chip testing and validation, * VLSI circuit and system design using Verilog, * Architecture design space exploration, * Spectrum Analyzer. Annual base salary for this role in California ...

Company Description Insilico is an End-to-End specialized VLSI, Embedded Design & Software services ... testing and verification techniques and Hands on with Scripting language [Perl/Python/Ruby] Good ...

Company Description Insilico is an End-to-End specialized VLSI, Embedded Design & Software services ... testing and verification techniques and Hands on with Scripting language [Perl/Python/Ruby] Good ...

Senior PDK Engineer

Santa Clara, CA · On-site

$168 - $264.50/hr

Understanding basic fab process, mask generation, testing and qualification. * Background of mosfet device behavior, CMOS layout, and VLSI design. * Great interpersonal skills * Passionate about ...

Senior GoLang Engineer

Oakland, CA · On-site

$140K - $185K/yr

Company Description Insilico is an End-to-End specialized VLSI, Embedded Design & Software services ... testing in the form of unit, integration, functional and load tests Follow Agile best practices ...

Senior GoLang Engineer

Oakland, CA · On-site

$140K - $185K/yr

Company Description Insilico is an End-to-End specialized VLSI, Embedded Design & Software services ... testing in the form of unit, integration, functional and load tests • Follow Agile best practices ...

Senior PDK Engineer

Santa Clara, CA · Hybrid

$126K - $164K/yr

Understanding basic fab process, mask generation, testing and qualification. * Background of mosfet device behavior, CMOS layout, and VLSI design. * Great interpersonal skills * Passionate about ...

Senior PDK Engineer

Santa Clara, CA · On-site

$126K - $164K/yr

Understanding basic fab process, mask generation, testing and qualification. * Background of mosfet device behavior, CMOS layout, and VLSI design. * Great interpersonal skills * Passionate about ...

Senior PDK Engineer

Santa Clara, CA · On-site

$170 - $310/hr

Understanding basic fab process, mask generation, testing and qualification. * Background of mosfet device behavior, CMOS layout, and VLSI design. * Great interpersonal skills * Passionate about ...

... testing. The ideal candidate will have proven experience with Automatic Test Equipment (ATE ... Understanding VLSI and semiconductor manufacturing process * Strong scripting skills in perl or ...

... testing. The ideal candidate will have proven experience with Automatic Test Equipment (ATE ... Understanding VLSI and semiconductor manufacturing process * Strong scripting skills in perl or ...

... VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Preferred Qualifications Highly motivated and passionate about SW/firmware testing. Proficiency in ...

... testing. The ideal candidate will have proven experience with Automatic Test Equipment (ATE ... Understanding VLSI and semiconductor manufacturing process * Strong scripting skills in perl or ...

... VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Preferred Qualifications Highly motivated and passionate about SW/firmware testing. Proficiency in ...

... testing. The ideal candidate will have proven experience with Automatic Test Equipment (ATE ... Understanding VLSI and semiconductor manufacturing process * Strong scripting skills in perl or ...

Strong debugging, testing, profiling, and code-structuring skills. * Ability to collaborate with ... PCB placement, PCB layout automation, EDA routing/placement, VLSI physical design, CAD/CAM ...

Wireless Design Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

... VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW ... random testing, and code/functional coverage. Verification experience of one or more of the ...

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Infographic showing various Vlsi Testing job openings in California as of August 2026, with employment types broken down into 1% As Needed, 88% Full Time, 8% Part Time, 2% Contract, and 1% Nights. Highlights an 87% Physical, 3% Hybrid, and 10% Remote job distribution.

Analog Design Engineer

OMNIVISION

Santa Clara, CA • On-site

$156K - $160K/yr

Full-time

Re-posted 2 days ago


Job description

•    Conduct end-to-end design and development of advanced CMOS Image Sensor (CIS) technologies with a focus on transistor-level design, simulation, and verification of analog circuits using Cadence Virtuoso. 
•    Design analog building blocks such as Analog Static RAM (ASRAM), ensuring support for complex readout formats including Dual Conversion Gain (DCG), Correlated Double Sampling (CDS), Correlated Multiple Sampling (CMS), and 4c2p. 
•    Perform complete schematic design flow, closely collaborate with layout engineers on device matching, symmetry, shielding, and routing for optimal noise performance and area efficiency. 
•    Carry out comprehensive post-layout verification, including Parasitic Extraction (PEX), Design Rule Check (DRC), Layout vs. Schematic (LVS), and Physical Electrical Rule Check (PERC) using Calibre.
•    Conduct system-level analog simulation and CIS signal chain verification to ensure correct signal propagation from pixel through the entire analog front-end to digital input interface.
•    Execute extensive process, voltage and temperature (PVT) and Monte Carlo simulations to evaluate functional robustness, and performance margins. 
•    Perform IR drop analysis and power integrity verification to ensure reliable power delivery and layout feasibility.
•    Utilize Analog FastSPICE (AFS), Empyrean ALPS, and NanoSpice for block-level and full-chain validation under realistic operating scenarios.
•    Develop and maintain automation scripts in Python and Perl to streamline simulation flow, including netlist generation, corner sweeping, batch result parsing, and yield analysis. Build scalable toolchains to support multi-corner, multi-mode simulations and regression testing, enhancing design turnaround and validation coverage.
•    Collaborate with cross-functional teams with digital design, verification, process, and test to define analog-digital interface specifications, establish timing constraints, support readout calibration algorithms, and debug post-silicon performance issues. 
•    Participate in design reviews, tapeout signoff, and lab characterization, contributing to silicon bring-up and performance optimization.
Requirements:
Master’s degree in Electrical Engineering, Computer Engineering, or a related field with advanced-level courses work in Analog Integrated Circuit, CMOS Circuit Design, RF Circuits and Systems Design, VLSI system design, and VLSI Signal Processing.
Must possess the following skills:
•    Analog circuits using MOS models,
•    Operational amplifier and current mirror design,
•    Noise analysis and feedback system,
•    Evaluation of offset distortion and nonlinearity,
•    Functional verification using ModelSim,
•    Static timing analysis, power and area estimation,
•    Standard-cell based logic and physical synthesis,
•    Hardware scheduling and retiming,
•    Number representation and digital arithmetic,
•    Full analog IC design flow,
•    Post-tapeout chip testing and validation,
•    VLSI circuit and system design using Verilog,
•    Architecture design space exploration,
•    Spectrum Analyzer.
Annual base salary for this role in California, US is expected to be between $156,853 - $160,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.