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Vlsi Physical Design Intern Jobs (NOW HIRING)

Tenstorrent University Jobs

$50/hr

As a Physical Design Intern, you'll work hands-on from synthesis through tapeout, collaborating ... Solid understanding of logic design, VLSI, and transistor-level concepts * Familiar with PnR tools ...

Apple

Physical Design Methodology CAD Engineer

Austin, TX · On-site

$134K - $138K/yr

Minimum Qualifications Knowledge of Tcl, Python or Perl scripting languages Minimum requirement of BS Preferred Qualifications Good understanding of VLSI / Physical Design basics through previous ...

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How much do vlsi physical design intern jobs pay per hour?

As of Aug 15, 2026, the average hourly pay for vlsi physical design intern in the United States is $19.38, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $21.63 per hour, depending on experience, location, and employer.

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Vlsi Physical Design Intern jobs near you

Senior VLSI Physical Design Integration Engineer

Fairygodboss

Westford, MA • On-site

$136 - $264.50/hr

Other

Posted 10 days ago

Job description

# Senior VLSI Physical Design Integration EngineerNVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life's work, to amplify human inventiveness and intelligence.NVIDIA is seeking an outstanding Senior VLSI Physical Design Integration Engineer who is dedicated to collaborating closely with our teams in the USA, Israel, and India. As a valued member of our team, you will contribute to the development of our networking product line, from concept to tapeout. If you are hardworking and thrive on challenges, join us and make a significant impact!**What you'll be doing:*** Run integration flows to build RTL, run connectivity checks, and assemble logical units.* Perform linting checks and debug RTL and netlist-level issues.* Collaborate with front-end teams to resolve connectivity issues and implement design fixes to ensure physically-viable RTL netlists are delivered to downstream physical design flows.* Project level cell library management to ensure compatibility between all workflows.* Run synthesis workflows and optimize for area, power, and timing.* Run physical design flow from netlist to GDS, perform STA, physical verification (LVS/DRC)* Perform netlist checks and formal equivalence validation.* Enhance tool automation, streamline workflows, and document best practices.**What we need to see:*** BSEE / MSEE or equivalent experience.* Minimum 5+ years of experience in VLSI physical design implementation on 16nm, 7nm, 5nm or 3nm technology.* Able to assist in design flow development and debugging.* Already a validated strong power user of P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys (ICC2/DC/PT/STAR/ICV), Cadence (Genus/Innovus/Tempus) and other major EDA companies.* To be successful you should possess strong analytical and debugging skills.* Proficiency using Python, Perl, Tcl, Make scripting is desired.* Great teammateNVIDIA is widely considered to be the leader of AI computing, and one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you.The base salary range is 136,000 USD - 264,500 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.You will also be eligible for equity and . NVIDIA accepts applications on an ongoing basis.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #J-18808-Ljbffr

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