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Vlsi Layout Design Engineer Jobs (NOW HIRING)

Ampere

Principal Layout Design Engineer

Durham, NC · Hybrid

$182K - $273K/yr

Coach and train junior engineers to foster skill development within the team. About you: * Minimum of 8 years' experience in custom layout design. * Current hands-on experience with 3nm technology is ...

Teledyne

Sr. ASIC Layout Design Engineer

Goleta, CA

$113K - $151K/yr

We are seeking an experienced Senior Analog/Mixed-Signal Layout Design Engineer to help develop the next generation of high-performance focal-plane array readout integrated circuits (ROICs). These ...

Lockheed Martin

PCB Layout Design Engineer

Orlando, FL · On-site

You will be the Printed Circuit Board (PCB) Layout Design Engineer for the Missiles & Fire Control (MFC) hardware development team. Our team delivers high density, high reliability electronics that ...

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Vlsi Layout Design Engineer information

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How much do vlsi layout design engineer jobs pay per year?

As of Jun 7, 2026, the average yearly pay for vlsi layout design engineer in the United States is $120,849.00, according to ZipRecruiter salary data. Most workers in this role earn between $90,000.00 and $144,000.00 per year, depending on experience, location, and employer.

What are some common challenges faced by VLSI Layout Design Engineers during the tape-out phase?

VLSI Layout Design Engineers often encounter tight deadlines and last-minute design changes during the tape-out phase, which can be challenging to manage. Ensuring design rule compliance, minimizing layout-versus-schematic (LVS) and design rule check (DRC) errors, and coordinating with verification and circuit design teams are key tasks. Effective communication and attention to detail are essential to resolve issues quickly and avoid costly delays. Additionally, balancing performance, power, and area constraints while meeting manufacturing requirements is a complex aspect of the role.

What does a VLSI Layout Design Engineer do?

A VLSI (Very-Large-Scale Integration) Layout Design Engineer is responsible for creating the physical layout of integrated circuits (ICs) using electronic design automation (EDA) tools. They translate circuit schematics into detailed geometric representations that can be manufactured on silicon chips, ensuring optimal performance, area, and power usage. Their work involves close collaboration with design, verification, and fabrication teams to meet the specifications and constraints of the project. Attention to detail and a strong understanding of semiconductor processes are essential in this role.

What is the difference between Vlsi Layout Design Engineer vs Vlsi Verification Engineer?

AspectVlsi Layout Design EngineerVlsi Verification Engineer
Primary FocusDesigning physical layouts of integrated circuitsVerifying functionality and performance of VLSI designs
Skills & CertificationsCAD tools, CMOS design, layout optimizationSimulation tools, verification methodologies, scripting
Work EnvironmentDesign teams, CAD environments, EDA toolsTesting labs, simulation environments, design validation
Industry UsageFoundries, chip design companies, semiconductor industryASIC/FPGA companies, verification service providers

While both roles are essential in VLSI chip development, the Vlsi Layout Design Engineer focuses on creating the physical layout of circuits, ensuring manufacturability and performance. In contrast, the Vlsi Verification Engineer concentrates on testing and validating the design to meet specifications. Both roles require specialized skills and often collaborate closely during chip development.

What are the key skills and qualifications needed to thrive as a VLSI Layout Design Engineer, and why are they important?

To thrive as a VLSI Layout Design Engineer, you need a strong background in semiconductor physics, integrated circuit (IC) design principles, and typically a degree in electrical or electronics engineering. Expertise in EDA tools such as Cadence Virtuoso, Mentor Graphics, and knowledge of DRC/LVS verification processes is essential. Attention to detail, problem-solving aptitude, and effective collaboration skills help ensure high-quality and efficient layout designs. These skills and qualities are crucial for creating reliable, manufacturable, and high-performance ICs in a fast-paced tech environment.
Infographic showing various Vlsi Layout Design Engineer job openings in the United States as of May 2026, with employment types broken down into 67% Full Time, 7% Part Time, 2% Temporary, and 24% Contract. Highlights an 84% Physical, 14% Hybrid, and 2% Remote job distribution, with an average salary of $120,849 per year, or $58.1 per hour.
Principal Layout Design Engineer

Principal Layout Design Engineer

Ampere Computing LLC

Santa Clara, CA • On-site

$182K - $273K/yr

Full-time

Medical, Dental, Vision, Retirement

Posted 9 days ago

Job description

Description
Invent the future with us.
Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AI compute.
As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications.
Join us at Ampere and work alongside a passionate and growing team - we'd love to have you apply!
About the role:
As a key member of the layout team, you will be responsible for delivering clean layouts that meet LVS, DRC, ERC, EM, and IR requirements.
Your role will involve close collaboration with various teams to ensure seamless full-chip integration and high-quality design implementation.
What you'll achieve:
  • Collaborate with the Place & Route (P&R) team to resolve full-chip integration issues.
  • Develop and improve methodologies to simplify custom macro integration into the P&R flow.
  • Floorplan and build out cells, blocks, and macros efficiently.
  • Understand, create, and debug LEF files to support design processes.
  • Design complex layouts for both analog and digital circuits using deep submicron technologies.
  • Analyze and interpret LVS, DRC, ERC, EM, and IR results to identify and resolve issues.
  • Identify schematic or layout problems and work closely with engineering teams to address them.
  • Ability to work on multiple projects across different technologies simultaneously.
  • Learn and effectively utilize Ampere's in-house design tools.
  • Coordinate with circuit engineers located in different regions and time zones.
  • Support and assist during tapeout phases to ensure successful project completion.
  • Contribute ideas as an integral part of a small, collaborative team.
  • Coach and train junior engineers to foster skill development within the team.

About you:
  • Minimum of 8 years' experience in custom layout design.
  • Current hands-on experience with 3nm technology is essential.
  • High proficiency in laying out custom digital components such as SRAM, register files, and standard cells.
  • Strong skills in designing custom analog blocks including amplifiers and resistor ladders.
  • Expertise in laying out and balancing custom clock H-trees for full-chip designs.
  • Experience with full-chip integration of custom IP alongside P&R teams.
  • Solid knowledge of Design for Manufacturability (DFM), hierarchical layout techniques, device matching, and low-parasitic layout practices.
  • Good understanding of Electromigration (EM) and IR drop analysis.
  • Proficient with Cadence XL/GXL/EXL and Mentor Graphics Calibre tools.
  • Familiarity with Cadence Innovus is a plus.
  • Experience with Totem tools for EM/IR analysis is advantageous.
  • Programming skills are a plus but not required.
  • Excellent communication skills with the ability to collaborate effectively across multiple locations and time zones.
  • Bachelor's degree & 8 years of related experience; or master's degree & 6 years; or PhD & 3 years

What we'll offer:
At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, cash long-term incentive, and comprehensive benefits.
The full base pay range for this role is between $182,000 and $273,000, except in the San Francisco Bay Area where the range is between $195,000 and $292,000.
Our benefits include health, wellness, and financial programs that support employees through every stage of life.
Benefit highlights include:
  • Premium medical insurance, dental insurance, vision insurance, as well as income protection and a 401K retirement plan, so that you can feel secure in your health and financial future.
  • Unlimited Flextime and 10+ paid holidays so that you can embrace a healthy work-life balance.
  • A variety of healthy snacks, energizing espresso, and refreshing drinks to keep you fueled and focused throughout the day.

And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are excited to share more about our career opportunities with you through the interview process.
#LI-TC
#LI-Hybrid
Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.

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