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Virtual Tester Jobs in California (NOW HIRING)

Generate and convert ATE patterns utilizing virtual tester environments to ensure high-fidelity translation from simulation. Google is proud to be an equal opportunity and affirmative action employer.

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CPU SoC Verification Engineer

San Diego, CA · On-site

$144K/yr

Generate and convert ATE patterns utilizing virtual tester environments to ensure high-fidelity translation from simulation. Information collected and processed as part of your Google Careers profile ...

... the Virtual Reality space. Our Client's team applies a range of software, computer vision and ... We are looking for someone with testing skills on mobile or standalone devices preferably Android ...

... the Virtual Reality space. Our Client's team applies a range of software, computer vision and ... We are looking for someone with testing skills on mobile or standalone devices preferably Android ...

#Virtual Platform Engineer

Santa Clara, CA · On-site

$111.30 - $166.90/hr

Lead design, coding, and testing efforts to ensure that projects are completed to specifications ... Experience developing Virtual Platforms or Simulators. Key Skills * SystemC TLM or QEMU. * Modern C+

Embedded Tester

San Jose, CA · On-site

$100 - $130/hr

Urgent position of Embedded Tester Engineer Location : San Jose, CA (On-site) The Opportunity Staff ... Build the virtual environment that mocks hardware behavior to test firmware and software logic.

New

Virtual Training Representative

Los Angeles, CA · On-site +1

$16.75 - $21.50/hr

Virtual Training Representative Department: Dealer Onboarding Employment Type: Full Time Location ... Display familiarity with UpdatePromise products and assist with UI testing. What do we absolutely ...

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CPU SoC Verification Engineer

Socket.dev

San Diego, CA • On-site

$138 - $197/hr

Other

Posted 3 days ago

New


Job description

Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 4 years of experience with ARM-based SoC verification, including cache coherency, Network-on-Chip (NoC) interconnects, or high-speed bus protocols.
  • Experience with post-silicon debug and diagnosing failures across Process, Voltage, and Temperature (PVT) corners.
  • Experience in RTL verification and Gate Level Simulation (GLS) workflows.
Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience with UVM/OVM methodologies and using Python or Perl to automate ARM SoC verification flows.
About the job:

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a CPU SoC DV Engineer, you will be responsible for ensuring the functional integrity of CPU subsystems from initial RTL simulation through to final silicon characterization. You will develop robust verification environments, drive GLS, and partner with ATE teams to debug and stabilize high-speed patterns in a production environment.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities:
  • Drive ARM SoC and sub-system level verification, simulation, and debug for CPU RTL and gate-level netlists.
  • Lead post-silicon debug efforts to diagnose complex hardware failures and ensure pattern stability in production.
  • Translate simulation-based functional sequences into ATE/SLT-ready formats, ensuring high-fidelity pattern conversion through virtual tester environments.
  • Execute GLS and timing-annotated (SDF) simulations using industry-standard EDA tools.
  • Generate and convert ATE patterns utilizing virtual tester environments to ensure high-fidelity translation from simulation.
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