Minimum qualifications
• B.S. degree in Computer Science or Electrical Engineering or equivalent experience.
• 7-10+ years of experience with 5+ years experience in hardware model simulation, virtual platform, performance modeling of complex SoCs or high-fidelity hardware accelerators.
• High proficiency in modern C++ in the domains of chip-design, electronic design automation or simulation.
• Experience with the SystemC/TLM library
• Experience with virtual platform development tools and frameworks, such as Synopsys Virtualizer, Cadence Virtual Platform, Imperas OVP, or ARM Fast Models
• Familiarity with processor/DSP architectures, such as ARM, RISC-V, and XTensa
• Familiarity with NoC, MMU, address translations, and cache modeling
• Familiarity with the standard C++ concurrency support library: threads, atomic operations, memory ordering, etc…
• Proficiency in Python to automate design flows, creation of collateral data