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Vhdl Verification Engineer Jobs (NOW HIRING)

Senior Verification Engineer

New York, NY ยท On-site

$114K - $157K/yr

Verify designs written in VHDL and support verification using Verilog/SystemVerilog. * Debug FPGA issues and collaborate with cross-functional engineering teams. * Work with Xilinx Vivado tools and ...

UVM SYSTEMVERILOG VERIFICATION ENGINEER

Warren, NJ ยท On-site

$141K/yr

Airspan Careers UVM SYSTEMVERILOG VERIFICATION ENGINEER Location: Warren, New Jersey, Plano, TX or ... Knowledge of FPGA development and hardware description languages such as VHDL/Verilog.

Wireless Radio Verification Engineer

San Diego, CA ยท On-site

$144K/yr

As a Wireless Radio Verification Engineer, you'll ensure first-time-right silicon success through ... Experience with digital design fundamentals Verilog or VHDL.Experience with scripting languages ...

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Showing results 1-20

Vhdl Verification Engineer information

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$80K

$142.6K

$203.5K

How much do vhdl verification engineer jobs pay per year?

As of Jun 16, 2026, the average yearly pay for vhdl verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a VHDL Verification Engineer, and why are they important?

To thrive as a VHDL Verification Engineer, you need a deep understanding of digital design principles, strong VHDL coding skills, and a background in electrical or computer engineering. Familiarity with simulation tools like ModelSim or Questa, experience with verification methodologies such as UVM, and knowledge of scripting languages are typically required. Attention to detail, problem-solving, and strong communication skills help you effectively identify design issues and collaborate with cross-functional teams. These competencies ensure robust verification processes, leading to reliable and efficient hardware designs.

What are some common challenges faced by VHDL Verification Engineers when collaborating with hardware design teams?

VHDL Verification Engineers often face challenges in ensuring thorough communication with hardware design teams, especially when design specifications change frequently or are not fully documented. Synchronizing testbench development with ongoing design modifications can be demanding, requiring proactive coordination and adaptability. Additionally, aligning on verification methodologies and effectively managing bug tracking and resolution are crucial to prevent delays and ensure high-quality deliverables. Strong collaboration skills and a proactive approach to cross-functional teamwork are key to overcoming these challenges.

What are VHDL Verification Engineers?

VHDL Verification Engineers are professionals who specialize in testing and validating digital hardware designs using VHDL (VHSIC Hardware Description Language). They develop testbenches, write simulation scripts, and ensure that digital circuits, such as FPGAs and ASICs, function correctly according to specifications. Their role is crucial in detecting design errors early in the development process, improving product reliability, and reducing costly hardware revisions. They often work closely with design engineers and use specialized verification tools to automate and streamline the testing process.
Infographic showing various Vhdl Verification Engineer job openings in the United States as of June 2026, with employment types broken down into 1% As Needed, 98% Full Time, and 1% Part Time. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.
VHDL Digital Engineer

$104 - $174/hr

Full-time

Posted 21 days ago


Job description

VHDL Digital Engineer | San Diego, California, United States
Indotronix is seeking an :Software Engineer-Test & Verification 4
Location:-San Diego California
Clearance: Active Secret

Job Description
Seeking a Senior FPGA Verification Lead Engineer to support the design verification and validation of FPGA-based software-defined radio and DoD communication systems. This role will provide hands-on technical leadership, mentor verification engineers, and drive FPGA verification activities throughout the product lifecycle.
Key Responsibilities
  • Lead and mentor a team of 2-4 VHDL verification engineers
  • Define and maintain FPGA and digital logic verification frameworks and architectures
  • Develop verification plans based on design requirements and technical specifications
  • Simulate, verify, and validate FPGA logic designs and system functionality
  • Analyze and debug simulation failures, identify root causes, and support issue resolution with design teams
  • Perform regression testing and generate verification metrics and status reports
  • Support FPGA product lifecycle activities including requirements, design, verification, and production release
  • Coordinate with cross-functional engineering teams and program management to ensure project execution and schedule compliance
  • Support technical planning, task estimation, forecasting, and schedule management
  • Participate in design reviews, verification reviews, and technical meetings

Required Skills
  • Strong experience in VHDL design and verification methodologies
  • Experience with FPGA-based DoD communication or software-defined radio systems
  • Experience developing verification plans, test benches, functional tests, and bus functional models
  • Proficiency with Siemens Questa Simulator
  • Strong analytical, troubleshooting, and debugging skills
  • Experience managing technical tasks, schedules, and deliverables
  • Strong communication and collaboration skills in a team environment
  • Ability to obtain and maintain a U.S. Security Clearance

Preferred Skills
  • Active Security Clearance
  • Experience leading FPGA verification teams
  • Experience with OSVVM verification methodology
  • Experience with Linux scripting languages such as Perl, TCL, Bash, or Makefile
  • Experience with Siemens formal verification tools including Lint, Inspect, and CDC
  • Experience with cost tracking and metric reporting
  • Ability to obtain Special Access Program clearances

Education / Experience
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field with typically 12+ years of professional experience in FPGA verification, digital logic design, or related engineering disciplines.

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About Indotronix

Sourced by ZipRecruiter

In 1986, Indotronix established itself in the staffing space. 22 years later, Avani entered the scene, offering consulting and technology development. Finally, in 2016, the two joined forces to begin delivering talent across all areas, from Staffing to Consulting to unique platform development.

Industry

Recruiting and staffing services

Company size

1,001 - 5,000 Employees

Headquarters location

Rochester, NY, US