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Verification Verilog Application Engineer Jobs (NOW HIRING)

Superbeo

Design Verification Lead Engineer

Austin, TX · On-site

Job Title : Design Verification Lead Engineer Job location: Austin, TX Job Duration: 3 Months ... Proficiency in C-shell scripting, Verilog-HDL & System Verilog. * Strong knowledge in SV Assertions ...

Apple

CPU Verification Engineer

Austin, TX · On-site

$134K/yr

Description As a CPU Verification Engineer owning the verification of a certain area of ... UVM and System Verilog will come a long way with us. - Apply knowledge of industry standard ...

CYNET SYSTEMS

Verification Engineer 3

Santa Clara, CA · On-site

$82 - $86/hr

Experience in Verilog/SystemVerilog/SystemC is preferred. * Experience in C/Verilog environment ... Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a ...

Concurrent

Field Application Engineer

Brea, CA · On-site

We're proud to be experts in what we do and are looking for a Field Application Engineer to join ... verify identity and eligibility to work in the United States and to complete the required ...

New

InterSources Inc.

Verification Engineer

Saratoga, CA · On-site

$150K/yr

Qualifications * ME/BE in Electrical Engineering, Computer Engineering, or related field ... Expertise in Hardware Verification and Hardware Verification Methodology (e.g., System Verilog, OVM ...

Apple

CPU DFT Verification Engineer

Santa Clara, CA · On-site

$159K/yr

Description As a CPU DFT Verification Engineer, you will have the following responsibilities: • ... Understanding of verification testplans, Verilog/System-Verilog testbenches, transactors and ...

Siemens

Field Application Engineer - PowerPro

Austin, TX · On-site

$146K - $293K/yr

Field Application Engineer - RTL Design / PowerPro Job Reference #: 508828 Job Location: Austin ... Verilog/SystemVerilog/VHDL) • Knowledge of digital design, synthesis, and verification flows • ...

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How much do verification verilog application engineer jobs pay per year?

As of Sep 15, 2026, the average yearly pay for verification verilog application engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

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Infographic showing various Verification Verilog Application Engineer job openings in the United States as of September 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $142,619 per year, or $68.6 per hour.

CPU Power Management Verification Engineer

Austin, TX • On-site

Socket.dev
Network Security • 1 - 10 employees
Learn more about Socket.devexternal

$134K/yr

Other

Posted 7 days ago

Job description

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! In this highly visible role, you will be at the center of a chip design effort collaborating with many teams, with a critical impact on getting functional products to millions of customers quickly. We are looking for a strong candidate to join our processor verification team focusing on Power Management and Clock Control verification.

Description

As a Processor Power Management Verification Engineer, you will have the responsibilities as follows:

  • Work closely with architecture and RTL designers on verifying the functionality correctness of the Power Management and Clock Control logic
  • Develop and execute test plans and schedules for the power management and clock control logic
  • Develop tests in Assembly, Scripts, System Verilog, or vectors according to test plans to drive testing in simulation and emulation environments
  • Root cause failures and propose potential solution to the design team
  • Work with silicon bringup team on developing tests that work in the emulation and FPGA environments. Aid silicon debug in related part of the design
  • Develop coverage monitors and analyze coverage to ensure all the test cases in the test plans are covered
  • Develop checkers or Verilog/System Verilog-base transactor to verify the design
  • Write assertions and apply formal verification to the design
Minimum Qualifications
  • Minimum BS
  • Experience with digital logic, micro-processor architecture, or power management architecture
  • Experience with digital design verification including knowledge of Verilog/System-Verilog based testbenches, transactors checkers
  • Programming skills include scripting languages such as Perl or Python
Preferred Qualifications
  • Master’s degree preferred
  • Experience in processor or power management architecture and verification
  • In-depth knowledge in design verification environments like random constraint verification and/or UVM base testbenches
  • Experience in system Verilog assertions or silicon bringup or UPF and low power simulation
  • Experience with advanced verification techniques such as formal verification is a plus
  • Advanced programming skills such as object orientated programming or CPU assembly language is a plus
  • Should be an extraordinary teammate with excellent communication skills with the ability to articulate complex design issues during verification effort
  • Be able to create and follow detailed work schedules and work independently on the verification efforts for a block/area of the design
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