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Trainee Well Integrity Engineer Jobs (NOW HIRING)

KBR, Inc.

Structural Integrity Engineer

Houston, TX · On-site

Structural Integrity Engineer KBR Consulting provides specialized consulting engineering services ... The engineer will also be expected to interface with clients during projects as well as assist in ...

KBR

Structural Integrity Engineer

Houston, TX · Hybrid

Structural Integrity Engineer KBR Consulting provides specialized consulting engineering services ... The engineer will also be expected to interface with clients during projects as well as assist in ...

Amphenol TCS

Power Integrity Engineer

Yocumtown, PA · On-site

We design and manufacture a wide range of innovative connectors as well as cable assemblies for ... Power Integrity Engineer Location: Valley Green, PA Amphenol High Speed Products Group is the ...

Cornelis Networks

Signal Integrity Engineer

Wayne, PA · On-site

$151K/yr

Cornelis Networks is hiring a talented Signal Integrity (SI) Engineer with some experience in ... well as disability and life insurance, a dependent care flexible spending account, accidental ...

Amphenol HSIO

Senior Signal Integrity Engineer

Nashua, NH · On-site

$105K - $144K/yr

Component development as well as customer support on new product introduction * Contribute to an established team of dedicated signal integrity engineers and engineers of other disciplines * Share ...

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Broadcom, Inc.

Signal Integrity Engineer

San Jose, CA · On-site

$141K - $226K/yr

We are seeking an experienced SI/PI engineer to develop our next generation products with a focus ... Pre-layout modeling of transceivers as well as signal and PDN networks. * Automate sign-off ...

Broadcom, Inc.

Signal Integrity Engineer

San Jose, CA · On-site

$141K - $226K/yr

We are seeking an experienced SI/PI engineer to develop our next generation products with a focus ... Pre-layout modeling of transceivers as well as signal and PDN networks. * Automate sign-off ...

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How much do trainee well integrity engineer jobs pay per hour?

As of Jun 6, 2026, the average hourly pay for trainee well integrity engineer in the United States is $21.15, according to ZipRecruiter salary data. Most workers in this role earn between $15.38 and $24.28 per hour, depending on experience, location, and employer.
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Trainee Well Integrity Engineer jobs near you
Infographic showing various Trainee Well Integrity Engineer job openings in the United States as of May 2026, with employment types broken down into 33% Full Time, 7% Part Time, and 60% Contract. Highlights an 96% Physical, 2% Hybrid, and 2% Remote job distribution, with an average salary of $43,990 per year, or $21.1 per hour.
SPE Signal Integrity Engineer

SPE Signal Integrity Engineer

OSI Engineering, Inc.

San Jose, CA • Hybrid

$180K - $230K/yr

Other

Posted 7 days ago

Job description

SPE Signal Integrity Engineer
A leading chip and silicon IP provider is looking to hire an outstanding Senior Principal Engineer with strong expertise in signal integrity and package design to join the Memory Interface Chips Business Unit engineering team in either San Jose, California or Johns Creek, Georgia. This is a unique opportunity to work alongside some of the brightest engineers and inventors in the world, developing cutting-edge products that help move and protect data faster and more securely.
In this full-time and highly visible role, you ll report directly to the VP of Engineering and work within the SI/PI team. You will be responsible for modeling, analysis, and simulation of signal and power integrity for high-performance DDR technologies operating at speeds of 12800+ MT/s.
Responsibilities:

  • Create SI/PI methodologies and work with the Design and SI teams to do SI/PI study and package design for the latest DDR product portfolio
  • Work with our design team and validation team to define specifications and system design requirements such as packaging and PCB routings, IC-PKG-BRD decoupling requirements, channel simulations and jitter sensitivity analysis
  • Provide guideline to design team based on SI/PI study and simulation and silicon correlation so that our products will have superior SI performance, i.e. best RMT scores
  • Work with our customers to do collaboration to find the optimum SI/PI solution
  • Help the team during debug and bring up in lab if needed

Requirements:

  • Solid background in SI/PI and package design to provide technical leadership to the team
  • Strong interpersonal skill to keep the team motivated and focused
  • MS or PhD in Electrical Engineering with 10+ years of industry experience in which at least a few years with exposure to DDR4/5
  • Prior experience in simulating high speed memory (DDR4, DDR5) and/or SERDES interfaces is required
  • Solid theoretical background and understanding in EM and transmission line theory is a must
  • Strong background and solid understanding of equalization techniques such as FIR/FFE/DFE/CTLE are required
  • Must understand package and PCB design, be able to edit APD/Allegro layout files. Know SI/PI driven BGA assignment methodology and be able to simulate for the trade-offs in the context of a system
  • Extensive experience in correlating simulation results with lab measurements using scopes, TDRs, VNAs etc.
  • Strong understanding of the server system, from CPUs to DRAMs on DIMM modules, is highly desirable
  • Know the mechanisms of crosstalk and jitter in source-synchronous interfaces and be able to include the effect of such losses into low BER simulations
  • Proficient with simulations using Spice and ADS
  • Experience with commercial EDA tools such as ADS, HFSS, Q3D/PowerSI
  • Familiarity with RedHawk/Totem or XcitePI and Virtuoso is a strong plus
  • Lab characterization experience of passive components, link margin, or noise using real time/sampling scopes and VNA/TDR is a big plus
  • Basic knowledge of circuits used in high-speed link design is preferred.
  • Excellent writing and presentation skills are essential as well as good communication skills to work with customers and cross-functional teams.
  • Must be an innovative, self-motivated individual, be able to manage and drive his projects, and must be a team player

Type: Fulltime and Hybrid work schedule
Location: San Jose, CA or Johns Creek, GA
Salary Range: $180K-230K (DOE)

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