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K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.

With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization.

We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design flow—from RTL handoff to GDSII—and collaborate closely with architecture, RTL design, DFT, and packaging teams. This role also involves managing external physical design partners, driving tool and flow decisions, and ensuring first-pass silicon success in advanced FinFET technologies. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting‑edge SoCs that will fly in space.

• Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign‑off.
• Develop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area (PPA).
• Collaborate with front‑end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration.
• Drive timing closure across multiple voltage and process corners, including sign‑off with foundry‑qualified tools.
• Partner with package, SI/PI, and test teams for package‑aware floorplanning and chip‑to‑board integration.
• Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards.
• Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.
• Support chip bring‑up and debug through close collaboration with post‑silicon and test teams.
• Support your product through production and spaceflight.

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in ASIC physical design for high‑performance SoCs.
• Proven end‑to‑end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens).
• Strong hands‑on experience with timing closure, IR drop analysis, and ECO implementation.
• Deep understanding of physical design constraints for multi‑clock, multi‑voltage, and hierarchical SoCs.
• Experience with advanced FinFET process nodes.
• Prior experience managing or coordinating offshore/outsourced PD teams or vendors.
• Familiarity with DFT integration, STA sign‑off, and power domain implementation (UPF/CPF).
• Excellent communication, leadership, and cross‑functional collaboration skills.
• Act as technical leader and subject‑matter expert helping to teach, grow, and mentor others in the team.

• Exposure to radiation‑hardened or space‑qualified ASICs.
• Experience with chip‑package co‑design or advanced packaging (2.5D/3D).
• Familiarity with physical design service vendor management or offshore collaboration.
• Experience driving tapeouts through TSMC.
• Experience with Gate‑All‑Around technologies.
• Experience working in cross‑functional, geographically distributed teams.

• Base salary range for this role is $190,000 – $280,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.

As defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a “U.S. Person.”

The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.

K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.