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Trainee Computer Chip Engineer Jobs in Fife, WA (NOW HIRING)

Axon

Senior Firmware Engineer I

Seattle, WA · On-site

$136K - $179K/yr

Collaborate with System-on-Chip (SoC) and Cellular Modem vendors to optimize for AIoT use-cases and ... B.S. in Computer Engineering, Computer Science, Electrical Engineering or equivalent * 8-14 years ...

K2 Space

Senior ASIC Emulation Engineer

Seattle, WA · On-site

$170K - $250K/yr

Build, integrate, and maintain full-chip, multi-chips and system-level emulation models on ... S. or M.S. in Electrical Engineering, Computer Engineering, or related field. * 5+ years of ...

Axon

Senior Firmware Engineer I

Seattle, WA · On-site

$136K - $179K/yr

Collaborate with System-on-Chip (SoC) and Cellular Modem vendors to optimize for AIoT use-cases and ... B.S. in Computer Engineering, Computer Science, Electrical Engineering or equivalent * 8-14 years ...

Targeted Talent

Compiler Tech Lead

Seattle, WA · On-site

$170K - $190K/yr

Our client is a company building the world's highest-performance pure-digital AI inference chip. We ... MS or PhD in Computer Science, Engineering or related field * 10+ years of experience developing ...

Nvidia

Senior GPU Memory Architect

Seattle, WA · On-site

Bachelor's degree (or equivalent experience) in Computer Engineering, Electrical Engineering ... An understanding in CPU or GPU architecture, memory systems, or network on-chip design.

Apple

Design Verification Engineer

Seattle, WA

$122K - $184K/yr

Description As part of a very dedicated team you will be at the heart of the chip design effort ... Preferred Qualifications Knowledge of computer architecture and digital design fundamentals ...

K2 Space

Senior ASIC Emulation Engineer

Seattle, WA

$170K - $250K/yr

Build, integrate, and maintain full-chip, multi-chips and system-level emulation models on ... S. or M.S. in Electrical Engineering, Computer Engineering, or related field. * 5+ years of ...

K2 Space

Senior ASIC Emulation Engineer

Seattle, WA · On-site

$170K - $250K/yr

Build, integrate, and maintain full-chip, multi-chips and system-level emulation models on ... S. or M.S. in Electrical Engineering, Computer Engineering, or related field. * 5+ years of ...

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Trainee Computer Chip Engineer information

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How much do trainee computer chip engineer jobs pay per hour?

As of Aug 22, 2026, the average hourly pay for trainee computer chip engineer in Fife, WA is $24.11, according to ZipRecruiter salary data. Most workers in this role earn between $19.86 and $28.12 per hour, depending on experience, location, and employer.
Trainee Computer Chip Engineer jobs near you

Senior ASIC Design Verification Engineer

K2 Space

Seattle, WA • On-site

$170K - $250K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 22 days ago

Job description

The Role 

We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Responsibilities 

  • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments. Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
  • Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
  • Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
  • Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
  • Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
  • Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
  • Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
  • Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
  • Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
  • Participate in ASIC team interviews.
  • Contribute to advancement of DV methodologies and improvements.
  • Engage external IP providers and verification partners when needed. 

Qualifications 

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 5+ years of experience in ASIC/SoC verification.
  • Solid understanding of SystemVerilog, digital logic, RTL design, and hardware verification flows.
  • Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tool, and scripting languages (ex: Python, Perl, TCL).
  • Experience with testplanning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
  • Experience with regression management, coverage analysis, revision control (Git), and CI/CD automation.
  • Understanding of several industry-standard interfaces (ex: APB/AHB/AXI).
  • Familiarity with embedded processor-based designs and firmware/bare metal coding (ex: C, C++). 

Nice to Have

  • Experience with developing and integrating reference models.
  • Understanding of low power verification.
  • Familiarity with gate-level simulation and analog behavioral models.
  • Involvement in post-silicon validation planning and execution.
  • Experience working in cross-functional, geographically distributed teams.
  • Experience in space, telecom, or RF/digital mixed systems is a plus. 

Compensation and Benefits:

  • Base salary range for this role is $170,000 - $250,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
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About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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