ASIC Engineer
New York, NY · On-site
$181K/yr
Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design ... Interested in using software engineering techniques to improve the hardware design process, and ...
ASIC Engineer
New York, NY · On-site
$181K/yr
Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design ... Interested in using software engineering techniques to improve the hardware design process, and ...
ASIC Engineer
New York, NY · On-site
$181K/yr
Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design ... Interested in using software engineering techniques to improve the hardware design process, and ...
ASIC Engineer
New York, NY · On-site
$181K/yr
Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design ... Interested in using software engineering techniques to improve the hardware design process, and ...
Hardware Engineer, RTL
New York, NY · On-site
$200K - $400K/yr
The Role As an RTL Design Engineer at Normal, you will design and verify the digital logic at the ... This work sits at the intersection of classical ASIC design, novel computing architectures, and a ...
Hardware Engineer, RTL
New York, NY · On-site
$200K - $400K/yr
The Role As an RTL Design Engineer at Normal, you will design and verify the digital logic at the ... This work sits at the intersection of classical ASIC design, novel computing architectures, and a ...
Staff Engineer, Digital Design Engineering
Elizabeth, NJ · On-site
$135 - $202/hr
About the Role ADI's Aerospace and Defense Sensors, Subsystems, & Space business unit has an open position for an experienced Staff Digital Design Engineer with a background in FPGA/ASIC RTL and ...
New
Staff Engineer, Digital Design Engineering
Elizabeth, NJ · On-site
$135 - $202/hr
About the Role ADI's Aerospace and Defense Sensors, Subsystems, & Space business unit has an open position for an experienced Staff Digital Design Engineer with a background in FPGA/ASIC RTL and ...
New
Senior Engineer, Digital Design Engineering
$127K - $175K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Partial telecommute benefit (2 days/week work from home). Requirements: Must have a Master's degree ...
Senior Engineer, Digital Design Engineering
$127K - $175K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Partial telecommute benefit (2 days/week work from home). Requirements: Must have a Master's degree ...
Senior Engineer, Digital Design Engineering
Somerset, NJ · On-site
$127K - $175K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Partial telecommute benefit (2 days/week work from home). Requirements: Must have a Master's degree ...
Senior Engineer, Digital Design Engineering
Somerset, NJ · On-site
$127K - $175K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Partial telecommute benefit (2 days/week work from home). Requirements: Must have a Master's degree ...
Collaborate closely with RTL, design verification, DFT, STA, library, and package teams to resolve ... Strong experience in physical design for ASIC/SoC development, including successful implementation ...
Collaborate closely with RTL, design verification, DFT, STA, library, and package teams to resolve ... Strong experience in physical design for ASIC/SoC development, including successful implementation ...
ASIC Physical Design Engineer
New York, NY · On-site
$148K - $153K/yr
About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test ... You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and ...
ASIC Physical Design Engineer
New York, NY · On-site
$148K - $153K/yr
About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test ... You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and ...
ASIC Physical Design Engineer
New York, NY · On-site
$148K - $153K/yr
About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test ... You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and ...
ASIC Physical Design Engineer
New York, NY · On-site
$148K - $153K/yr
About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test ... You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and ...
... engineers with experience in both software and hardware design to help us build our FPGA or ASIC ... Your day-to-day work will predominantly involve OCaml & Hardcaml, for both RTL design and testing ...
... engineers with experience in both software and hardware design to help us build our FPGA or ASIC ... Your day-to-day work will predominantly involve OCaml & Hardcaml, for both RTL design and testing ...
... engineers with experience in both software and hardware design to help us build our FPGA or ASIC ... Your day-to-day work will predominantly involve OCaml & Hardcaml, for both RTL design and testing ...
... engineers with experience in both software and hardware design to help us build our FPGA or ASIC ... Your day-to-day work will predominantly involve OCaml & Hardcaml, for both RTL design and testing ...
Senior Engineer, Physical Design Engineering (ASIC)
Somerset, NJ · On-site
$143K - $147K/yr
Collaborate closely with RTL, design verification, DFT, STA, library, and package teams to resolve ... Strong experience in physical design for ASIC/SoC development, including successful implementation ...
Senior Engineer, Physical Design Engineering (ASIC)
Somerset, NJ · On-site
$143K - $147K/yr
Collaborate closely with RTL, design verification, DFT, STA, library, and package teams to resolve ... Strong experience in physical design for ASIC/SoC development, including successful implementation ...
Hardware Engineer, FPGA
New York, NY · On-site
$200K - $400K/yr
As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early ...
Hardware Engineer, FPGA
New York, NY · On-site
$200K - $400K/yr
As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early ...
... both RTL design and testing/integration. If you'd like to learn more, you can read about our ... Comfortable with a software programming language * Experienced with a Hardware Description (or ...
... both RTL design and testing/integration. If you'd like to learn more, you can read about our ... Comfortable with a software programming language * Experienced with a Hardware Description (or ...
... both RTL design and testing/integration. If you'd like to learn more, you can read about our ... Comfortable with a software programming language * Experienced with a Hardware Description (or ...
... both RTL design and testing/integration. If you'd like to learn more, you can read about our ... Comfortable with a software programming language * Experienced with a Hardware Description (or ...
THW Client Co-op
New York, NY · On-site
$27 - $37.50/hr
RTL design and verification of digital blocks, cores, and subsystems for ASIC products and FPGA ... Engineering - Previous experience with ASIC or FPGA development, as well as knowledge of and ...
THW Client Co-op
New York, NY · On-site
$27 - $37.50/hr
RTL design and verification of digital blocks, cores, and subsystems for ASIC products and FPGA ... Engineering - Previous experience with ASIC or FPGA development, as well as knowledge of and ...
Two Sigma Securities, Hardware Engineer
New York, NY · On-site
$165K - $300K/yr
... preferred in RTL design and verification for ASIC or FPGA * BS or MS in Computer Science ... Engineering, or a related field * Strong RTL design, optimization, and debugging skills, with ...
Two Sigma Securities, Hardware Engineer
New York, NY · On-site
$165K - $300K/yr
... preferred in RTL design and verification for ASIC or FPGA * BS or MS in Computer Science ... Engineering, or a related field * Strong RTL design, optimization, and debugging skills, with ...
Hardware Engineer, Physical Design
New York, NY · On-site
$200K - $400K/yr
Sitting at the intersection of custom ASIC design and our hardware-algorithm co-designed systems ... Collaborate closely with RTL, architecture, and DFT teams to influence early floorplanning, macro ...
Hardware Engineer, Physical Design
New York, NY · On-site
$200K - $400K/yr
Sitting at the intersection of custom ASIC design and our hardware-algorithm co-designed systems ... Collaborate closely with RTL, architecture, and DFT teams to influence early floorplanning, macro ...
FPGA Design Engineer
Hoboken, NJ · On-site
$134K - $185K/yr
FPGA Design Engineer Location: Hoboken, NJ Division : Technology Department: Engineering Reports to ... Develop RTL code for use within multiple projects. Analyze and enhance efficiency, scalability, and ...
FPGA Design Engineer
Hoboken, NJ · On-site
$134K - $185K/yr
FPGA Design Engineer Location: Hoboken, NJ Division : Technology Department: Engineering Reports to ... Develop RTL code for use within multiple projects. Analyze and enhance efficiency, scalability, and ...
FPGA Design Engineer
Hoboken, NJ · On-site
$134K - $185K/yr
FPGA Design Engineer Location: Hoboken, NJ Division : Technology Department: Engineering Reports to ... Develop RTL code for use within multiple projects. Analyze and enhance efficiency, scalability, and ...
FPGA Design Engineer
Hoboken, NJ · On-site
$134K - $185K/yr
FPGA Design Engineer Location: Hoboken, NJ Division : Technology Department: Engineering Reports to ... Develop RTL code for use within multiple projects. Analyze and enhance efficiency, scalability, and ...
Telecommute Asic Rtl Design Engineer information
See Murray Hill, NJ salary details
$98.9K - $109.3K
16% of jobs
$109.3K - $119.6K
3% of jobs
$119.6K - $129.9K
4% of jobs
$133K is the 25th percentile. Wages below this are outliers.
$129.9K - $140.3K
6% of jobs
The median wage is $146.8K / yr.
$140.3K - $150.6K
33% of jobs
$150.6K - $161K
3% of jobs
$161K - $171.3K
2% of jobs
$178.1K is the 75th percentile. Wages above this are outliers.
$171.3K - $181.6K
12% of jobs
$181.6K - $192K
5% of jobs
$192K - $202.3K
4% of jobs
$202.3K - $212.6K
12% of jobs
$98.9K
$158.1K
$212.6K
How much do telecommute asic rtl design engineer jobs pay per year?
As of Aug 20, 2026, the average yearly pay for telecommute asic rtl design engineer in Murray Hill, NJ is $158,097.00, according to ZipRecruiter salary data. Most workers in this role earn between $138,400.00 and $189,500.00 per year, depending on experience, location, and employer.
What is a telecommute ASIC RTL design engineer?
A Telecommute ASIC RTL Design Engineer is a professional who specializes in designing digital circuits at the Register Transfer Level (RTL) for Application-Specific Integrated Circuits (ASICs), while working remotely. They use hardware description languages like Verilog or VHDL to create and verify circuit designs tailored to specific applications. Their responsibilities often include developing, simulating, and optimizing digital logic, collaborating with cross-functional teams, and ensuring that the final silicon meets design specifications. Since the role is telecommute, all work is performed from a remote location using digital communication and collaboration tools.
What are the key skills and qualifications needed to thrive as a telecommute ASIC RTL design engineer?
To thrive as a Telecommute ASIC RTL Design Engineer, you need a strong background in digital logic design, proficiency in hardware description languages like Verilog or VHDL, and typically a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys or Cadence, as well as experience with simulation, synthesis, and debugging environments, is essential. Strong problem-solving abilities, attention to detail, and effective communication skills are crucial for collaborating remotely and ensuring design accuracy. These skills are vital to deliver complex, high-performance ASICs on schedule while working efficiently in a remote setting.
What are some common challenges faced by telecommute ASIC RTL design engineers, and how can they be addressed?
Telecommute ASIC RTL Design Engineers often face challenges like coordinating effectively with remote teams, ensuring version control integrity, and maintaining clear communication on project specifications. These challenges can be mitigated by utilizing robust collaboration tools, adhering to standardized documentation practices, and scheduling regular virtual meetings for design reviews. Additionally, staying proactive in seeking feedback and clarifying requirements helps ensure alignment and prevents costly design iterations.
What is the difference between Telecommute Asic Rtl Design Engineer vs Telecommute Digital IC Design Engineer?
| Aspect | Telecommute Asic Rtl Design Engineer | Telecommute Digital IC Design Engineer |
|---|---|---|
| Credentials | Bachelor's or Master's in Electrical Engineering or Computer Engineering; experience with RTL coding | Bachelor's or Master's in Electrical Engineering or Computer Engineering; experience with digital circuit design |
| Work Environment | Remote, primarily designing RTL code for ASICs | Remote, focusing on digital IC architecture and design |
| Industry Usage | Common in semiconductor and electronics companies |
Both roles often require similar educational backgrounds and work remotely in the semiconductor industry. The main difference lies in their focus: RTL Design Engineers concentrate on writing RTL code for ASICs, while Digital IC Design Engineers work on broader digital circuit architecture. Candidates should choose based on their specific skills and career interests in digital design or RTL coding.
What cities near Murray Hill, NJ are hiring for Telecommute Asic Rtl Design Engineer jobs?
Cities near Murray Hill, NJ with the most Telecommute Asic Rtl Design Engineer job openings:
Job description
About the Position
We are looking to hire an experienced ASIC Engineer to help us design, test and deploy advanced hardware designs. As part of our Ultra Low Latency team, you'll have the opportunity to collaborate with people in areas across the firm, including trading, networking and research infrastructure. We are looking for someone who can contribute to all of our projects and be happy to work on both FPGA-based and ASIC-based technologies.
We're big believers in the ability of tools to improve the productivity, reliability and day-to-day joy of hardware engineering. That's why we created Hardcaml, a hardware development toolchain embedded in OCaml. We don't expect you to know OCaml (we'll teach you here), but we are looking for hardware engineers who are excited about the advantages that better tools can bring, and are willing to try new things as a result.
About You
If you're a recruiting agency and want to partner with us, please reach out to agency-partnerships@janestreet.com.
We are looking to hire an experienced ASIC Engineer to help us design, test and deploy advanced hardware designs. As part of our Ultra Low Latency team, you'll have the opportunity to collaborate with people in areas across the firm, including trading, networking and research infrastructure. We are looking for someone who can contribute to all of our projects and be happy to work on both FPGA-based and ASIC-based technologies.
We're big believers in the ability of tools to improve the productivity, reliability and day-to-day joy of hardware engineering. That's why we created Hardcaml, a hardware development toolchain embedded in OCaml. We don't expect you to know OCaml (we'll teach you here), but we are looking for hardware engineers who are excited about the advantages that better tools can bring, and are willing to try new things as a result.
About You
- Have 4+ years practical experience in RTL design and verification
- Experienced in ASIC design using either Synopsys or Cadence flows, including at least one of the following:
- Front-end RTL design and synthesis
- Back-end physical design
- Verification (including formal)
- Interested in using software engineering techniques to improve the hardware design process, and experience programming in some high-level languages (Python, C++, Java, Haskell, etc.)
If you're a recruiting agency and want to partner with us, please reach out to agency-partnerships@janestreet.com.
About Jane Street
Sourced by ZipRecruiter
Industry
Finance and insurance
Company size
1,001 - 5,000 Employees
Headquarters location
New York, NY, US
Year founded
2000