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We are seeking a Senior Power Modeling Engineer to drive pre-silicon power modeling and analysis for AMD’s next-generation Embedded x86 SoC platforms. This role plays a critical part in defining use-case-driven power expectations, building SoC-level power models from IP inputs, and enabling informed EDC/TDC, voltage-frequency (VF), and PPA trade-off decisions early in the design cycle.

The ideal candidate brings deep hands‑on experience with SoC power modeling methodologies and understands how IP-level power characteristics scale to full-chip behavior. This engineer will collaborate closely with SoC architects, power architects, performance teams, and silicon validation teams to ensure accurate power projections and influence architectural direction.

• Develop and maintain SoC-level power models for Embedded x86 platforms using IP-level inputs (CPU, GPU, fabric, memory, and I/O).
• Create use-case-driven power models representing automotive, industrial, edge computing, and customer-specific embedded workloads.
• Translate real-world workloads into model inputs such as activity factors, concurrency, residency, and DVFS states.

• Build and maintain Voltage-Frequency (VF) curves across operating corners.
• Derive and validate EDC / TDC / current limits based on modeled workloads and platform constraints.
• Perform sensitivity studies across frequency, voltage, workload mix, and power states.

• Integrate IP-level power models into cohesive SoC-level frameworks.
• Ensure consistency of assumptions across IPs (clocking, power states, gating, DVFS).
• Identify gaps, inconsistencies, or inaccuracies in IP models and drive closure with IP teams.

• Partner with SoC and power architects to influence early architectural decisions.
• Evaluate power/performance/area trade-offs for new features, configurations, and SKUs.
• Support bounding-box analysis and product positioning decisions.

• Support pre-silicon to post-silicon correlation of power models.
• Refine models using silicon data, profiling, and validation feedback.
• Improve modeling methodologies, accuracy targets, and documentation.

• Professional experience in power modeling, power estimation, or SoC power analysis
• Strong understanding of:
  • SoC power architecture and DVFS
  • Static vs dynamic power components
  • EDC / TDC / electrical and thermal constraints
• Hands‑on experience building SoC-level power models from IP-level models
• Experience creating and analyzing VF curves
• Experience with Embedded or Automotive SoCs
• Familiarity with x86 CPU, GPU, memory, and fabric power behaviors
• Exposure to power modeling tools, spreadsheets, or internal frameworks used for pre-silicon estimation
• Experience with workload-driven modeling and benchmark abstraction
• Strong analytical and scripting skills (Python preferred)
• Ability to work across architecture, IP, performance, and validation teams
• Prior involvement in power correlation with silicon
• Ability to clearly communicate modeling assumptions and results to senior technical stakeholders

BS/MS in Electrical Engineering, Computer Engineering, or related field

Austin, TX

This role is not eligible for visa sponsorship.

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AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.

This posting is for an existing vacancy.