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Systemc Engineer Jobs (NOW HIRING)

Retym

Senior System C Engineer

Austin, TX · On-site

$99K - $135K/yr

Description We are seeking an experienced SystemC Engineer to join our ASIC development team. The ideal candidate will have a strong background in SystemC modeling, digital signal processing (DSP ...

CYNET SYSTEMS

Verification Engineer 3

Santa Clara, CA · On-site

$82 - $86/hr

Experience in Verilog/SystemVerilog/SystemC is preferred. * Experience in C/Verilog environment ... Object Oriented programming. * STL. * Computer architecture. * Data structures. * Perl. * Makefiles.

Mythic

Architecture Modeling Engineer

Palo Alto, CA

$120K - $225K/yr

Create cycle-accurate models of the hardware (C++/SystemC). * Collaborate with peer engineering teams to co-design and co-verify the hardware implementation. * Investigate new architectural ideas ...

Mythic

Architecture Modeling Engineer

Austin, TX

$120K - $225K/yr

Create cycle-accurate models of the hardware (C++/SystemC). * Collaborate with peer engineering teams to co-design and co-verify the hardware implementation. * Investigate new architectural ideas ...

CYNET SYSTEMS

Verification Engineer 3

Santa Clara, CA · On-site

$82 - $86/hr

Experience in Verilog/SystemVerilog/SystemC. * Experience in C/Verilog environment using DPI/PLI. Skills: * C. * C++. * Linux. * Gdb. * Valgrind. * Object Oriented programming. * STL. * Computer ...

Mythic

Architecture Modeling Engineer

Austin, TX

$120K - $225K/yr

Create cycle-accurate models of the hardware (C++/SystemC). * Collaborate with peer engineering teams to co-design and co-verify the hardware implementation. * Investigate new architectural ideas ...

Mythic

Architecture Modeling Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

Create cycle-accurate models of the hardware (C++/SystemC). * Collaborate with peer engineering teams to co-design and co-verify the hardware implementation. * Investigate new architectural ideas ...

Mythic

Architecture Modeling Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

Create cycle-accurate models of the hardware (C++/SystemC). * Collaborate with peer engineering teams to co-design and co-verify the hardware implementation. * Investigate new architectural ideas ...

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How much do systemc engineer jobs pay per year?

As of Sep 10, 2026, the average yearly pay for systemc engineer in the United States is $115,864.00, according to ZipRecruiter salary data. Most workers in this role earn between $83,000.00 and $151,500.00 per year, depending on experience, location, and employer.

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Infographic showing various Systemc Engineer job openings in the United States as of July 2026, with employment types broken down into 96% Full Time, 1% Part Time, and 3% Contract. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $115,864 per year, or $55.7 per hour.

Senior System C Engineer

Austin, TX • On-site

Retym
See more jobs at Retymexternal

$99K - $135K/yr

Full-time

Posted 24 days ago

Job description

Description
We are seeking an experienced SystemC Engineer to join our ASIC development team. The ideal candidate will have a strong background in SystemC modeling, digital signal processing (DSP), and ASIC development flows. This role involves developing high-level SystemC models, translating DSP algorithms into efficient SystemC implementations, and working closely with architecture, System, RTL, verification, and algorithm teams to enable system-level modeling and verification.
Requirements
Responsibilities
* Develop and maintain high-performance SystemC models for complex optical systems and ASIC designs.
* Translate DSP algorithms from MATLAB into accurate and efficient SystemC implementations.
* Translate optical systems modeling into SystemC models
* Collaborate with architecture, RTL, and verification teams throughout the ASIC development lifecycle.
* Develop executable reference models for architecture exploration and functional validation.
* Support verification environments by integrating SystemC models into mixed-language simulation environments.
* Analyze and optimize model performance while ensuring functional accuracy.
* Debug and resolve functional issues across system-level.
* Participate in architecture definition, design reviews, and technical discussions.
Required Qualifications
* Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
* Minimum 5 years of experience in SystemC development.
* Strong proficiency in SystemC, C++, and Transaction-Level Modeling (TLM).
* Experience with ASIC design and verification environments.
* Experience translating DSP algorithms from MATLAB to SystemC.
* Knowledge of digital signal processing concepts and fixed-point arithmetic.
* Hands-on experience with communication interfaces, including:
* Ethernet
* DSP-based communication systems
* Optical links/high-speed serial interfaces
* Strong debugging, analytical, and problem-solving skills.
* Excellent communication skills and ability to work in cross-functional engineering teams.
Preferred Qualifications
* Experience with UVM and SystemVerilog verification environments.
* Familiarity with RTL design (Verilog/SystemVerilog/VHDL).
* Experience with high-speed networking or communication ASICs.
* Knowledge of scripting languages such as Python or Perl.
* Experience with performance modeling and architectural exploration.
* Familiarity with version control systems (Git) and continuous integration workflows.
Desired Skills
* Strong system-level thinking and architectural understanding.
* Ability to work independently while collaborating across multidisciplinary teams.
* Attention to detail with a focus on model accuracy and maintainability.
* Passion for solving complex technical challenges in ASIC and communication system development.

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