ZipRecruiter

Log In

1

Sta Static Timing Analysis Engineer Jobs in Phoenix, AZ

PowerLattice

Principal Digital Design Engineer

Chandler, AZ · On-site +1

$200K - $250K/yr

Head of Engineering About Us PowerLattice is a well-funded semiconductor start-up company backed by ... Static timing analysis (STA) and timing closure * Timing constraint development and debug (SDC)

Intelliswift Software

Physical Design Engineer

Phoenix, AZ · On-site

$135K - $139K/yr

... static timing analysis, IR Drop, EM, & physical verification in advanced technology nodes Resolve design & flow issues related to physical design, identify potential solutions, & drive execution ...

Inherent Technologies

Design Verification

Chandler, AZ · Remote

$139K - $169K/yr

Good understanding of RTL synthesis , Static Timing Analysis & LEC Flows. Experience with flow optimizations such as Grey/Black-boxing techniques Good at communicating requirements/issues with ...

Cirrus Logic

DFT Engineer (CE-64000920)

Chandler, AZ · On-site

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Experience with synthesis, static timing analysis, and developing timing constraints. * Strong oral ...

next page

Showing results 1-20

All JobsSta Static Timing Analysis Engineer JobsSta Static Timing Analysis Engineer Jobs in Phoenix, AZ

Sta Static Timing Analysis Engineer information

See Phoenix, AZ salary details

$25

$53

$76

How much do sta static timing analysis engineer jobs pay per hour?

As of Aug 17, 2026, the average hourly pay for sta static timing analysis engineer in Phoenix, AZ is $53.25, according to ZipRecruiter salary data. Most workers in this role earn between $42.98 and $61.83 per hour, depending on experience, location, and employer.

What is a STA static timing analysis engineer?

STA (Static Timing Analysis) Engineers are specialists in the semiconductor industry who analyze and verify the timing performance of digital circuits without requiring dynamic simulation. They use specialized software tools to ensure that signal transitions occur within required time constraints, preventing issues like data corruption or circuit malfunction. Their work is crucial in the design and validation stages of integrated circuits (ICs), helping to guarantee that chips will function reliably at specified speeds and under different conditions.

What are the key skills and qualifications needed to thrive as a STA static timing analysis engineer?

To thrive as a Static Timing Analysis Engineer, you need a solid background in digital circuit design, timing concepts, and typically a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys PrimeTime, Cadence Tempus, and scripting languages like TCL or Perl is essential. Strong problem-solving abilities, attention to detail, and effective communication skills set top performers apart in this role. These competencies ensure accurate timing verification, efficient collaboration, and successful delivery of complex semiconductor projects.

What are some common challenges faced by STA static timing analysis engineers during project cycles?

STA Static Timing Analysis Engineers often encounter challenges related to tight project deadlines and complex design specifications. Balancing multiple design corners, managing timing closure for increasingly smaller technology nodes, and coordinating with physical design, synthesis, and verification teams are key hurdles. Additionally, staying updated with evolving EDA tools and methodologies is essential to ensure accurate analysis. Effective communication and troubleshooting skills are critical to resolve timing violations and deliver high-quality silicon on schedule.

What are popular job titles related to Sta Static Timing Analysis Engineer jobs in Phoenix, AZ?

For Sta Static Timing Analysis Engineer jobs in Phoenix, AZ, the most frequently searched job titles are:

What job categories do people searching Sta Static Timing Analysis Engineer jobs in Phoenix, AZ look for?

The top searched job categories for Sta Static Timing Analysis Engineer jobs in Phoenix, AZ are:

Sta Static Timing Analysis Engineer jobs near you

SOC Physical Design Static Timing Analysis Engineer

Intel

Phoenix, AZ • On-site

$164K - $311K/yr

Full-time

Medical, Retirement, PTO

Re-posted 20 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

19th of 157 rated electronics manufacturers

Job description

Job Details:Job Description: 

As a Physical Design Timing Engineer, you will play a pivotal role in shaping the performance, power efficiency, and functionality of Intel's cutting-edge System-on-Chip (SoC) designs. Your expertise will directly impact product quality, enabling groundbreaking advancements in technology that drive computing innovation. Collaborating across multiple teams, you will contribute to the creation and optimization of high-performance, low-power solutions while developing methodologies that enhance efficiency and operational excellence. This is an exciting opportunity to work on complex designs that have a global impact, delivering solutions that power today's world and inspire tomorrow's possibilities.

Key Responsibilities:

  • Perform SOC level timing analysis and optimization, ensuring designs meet functional and performance requirements.
  • Generate and verify timing constraints while addressing timing violations at the chip or block level for SoCs.
  • Conduct timing rollups and develop optimized clock networks for functionality, performance, and power efficiency.
  • Define methodologies to produce high-quality timing models and enable efficient physical design execution.
  • Establish the appropriate process, voltage, and temperature (PVT) conditions for timing analysis, aligning with product plans, and binning strategies.
  • Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning.
  • Collaborate with architecture, clocking design, DFT and logic design teams to develop flows for chip integration and validate clock network performance guidelines.
  • Contribute to the development of tools, flows, and methodologies that enhance SoC physical design and timing processes.
Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Minimum Qualifications

  • Bachelor's degree with 8 +years or master's degree with 6+ years or PhD with 4+ years in Electrical Engineering or Computer Engineering or Computer Science or a related field.
  • 7+ years technical proficiency in SOC level static timing analysis, clock network design, and timing closure methodologies.
  • 3+ years of experience with the following skills:
  • Strong expertise in timing constraint adaptation, physical design knowledge, and optimization techniques.
  • Proficiency with industry-standard tools for timing analysis, extraction, and physical design.
  • Familiarity with TCL scripting and timing budgeting processes.

Preferred Skills/Experience:

  • Demonstrated ability to collaborate across diverse teams and drive innovative solutions for SoC designs.
  • Experience with SoC clocking methodologies, disciplined execution, and problem-solving in digital design.
  • Knowledge of tools, flows, and methodologies for high-performance physical design.
  • Strong communication skills and ability to articulate technical concepts effectively.
  • DFT architecture knowledge is a strong plus
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Arizona, PhoenixAdditional Locations:US, California, Santa ClaraPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $164,470.00-311,890.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

What Intel employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom

Intel logo

About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

View All Intel Jobs

Apply